Fetch Decode Execute cycle

• What is the Fetch-Decode-Execute Cycle? 

  The fetch-decode-execute cycle is the process that the CPU goes through repeatedly to process instructions 
• There are 3 stages of FDE cycle:

  - Fetching an instruction from memory - supplying the address and receiving the instruction from memory

  - Decoding the instruction - interpreting the instruction and then reading and retrieving the required data from their addresses 

  - Executing the instruction - the CPU carries out the required action 
• Fetch 

  • The PC is loaded with 0 
  • The value from the PC (0) is copied to the MAR 
  • The data from the MAR (0) is sent across the address bus with the instruction to read the data sent across the control bus 
  • The data from that location in memory (0) is sent down the data bus to the MDR  
  • The PC is incremented by 1
• Decode 

  • The data is sent from the MDR to the CIR where it is split into the opcode and operand 
  • This is sent to the CU to be decoded 
• Execute #1

  • Which registers are used here will depend on the instruction being executed 
  • If a value is being inputted (INP) the ACC will store the value 
  • If a value is being outputted (OUT) this will be the value currently in the ACC 
  • If a value is loaded from RAM (LDA) this will be sent across the data bus from RAM (in the address location in the MAR) to the MDR 
• Execute #2

  • If a value is to be stored (STA) it will take the value from the ACC, send it to the MDR and then send it across the data bus to RAM (to the address location in the MAR) 
  • If a value is being added to or subtracted from another value (ADD/SUB)  
  • If the LMC code is to branch (BRA/BRZ/BRP) the comparison will take place in the ALU