Paging and TLB OS

• What is paging in memory management?

  A non-contiguous memory management scheme
• How does paging avoid external fragmentation?

  By breaking memory into small fixed-size blocks
• What are frames in memory management?

  Physical locations of memory managed by hardware
• What defines the page size in a computer system?

  Defined by computer architecture, typically a power of 2
• What is the relationship between page size and page tables?

  Smaller pages require larger page tables
• What are the steps of how paging happens?

  1. CPU generates a logical address (page number + offset)
  2. OS maintains a page table with base addresses
  3. Page number looks up frame in page table, offset added to base address for physical address
• What is the overhead associated with paging?

  Maintaining a page table requires additional memory
• What does translation time refer to in paging?

  Time taken for address translation via page table
• What are the components of page table entries?

  1. Frame number
  2. Valid bit
  3. Protection bit
  4. Referenced bit
  5. Cache control bit
  6. Dirty bit
• What is a Translation Lookaside Buffer (TLB)?

  A fast hardware implementation of page table lookup
• What happens when the TLB is full during a TLB miss?

  An entry is evicted using first in first out
• are frames and pages the same size?

  yes therefore any page will fit into any avaliable frame
• The virtual address generated by the CPU allows for the illusion of what

  Contiguous address space
• What is a page

  a page is a fixed size block of logical memory
• Using larger pages can sometimes cause what ?

  Fragmentation because of wasted memory if processes are small
• what is the formula for the number of pages calculation

  number of pages = address space/ page size
• What does the logical address contain ?

  page number and offset.
• what is an offset ?

  The offset found in the logical address specifies the exact location of the page in physical memory.
• What is the formula to translate a logical address to a physical address?

  Translation = offset + base address = physical address.
• external fragmentation does not occur because...

  pages and frames are the same size so no memory is split.
• What is the formula for a physical address without the logical address ?

  physical address = frame number x page size + offset
• Each page table is kept where?

  Main memory (RAM)
• How many memory addresses does paging require and why ?

  in paging every process requires 2 memory addresses, one is for the page table and the other is for the data/instruction.
• Why is it bad that paging requires 2 memory addresses

  because process speeds are doubled and memory use is doubled
• what is the solution to the problem of 2 memory addresses

  Caching the specific cache used for page tables is TLB.
• What is TLB 


  Translation lookaside buffer is a fast hardware implementation that allows the CPU to avoid the need to fetch instructions from main memory. like a shortcut to save time and resources.
• What is a TLB hit

  The page has been accessed before and is saved in the TLB so translation steps can be skipped (there's no need for the CPU to go and fetch it from main memory (take the scenic route)
• What happens in a TLB miss

  if the page is not in the TBL its a miss so the CPU must take the scenic route to the page table in main memory this is called page table look up.
• What does it mean if the page table look up fails ?

  this means the requested page is not in the page table and needs to be loaded from the hard drive this is called a page fault
• What is a Page fault ?

  When the CPU tries to access a page that is not in the main memory.
• What data can be found in page table entries ?

  • frame number
  • valid bit
  • protection bit
  • referenced bit
  • cache control bit
  • dirty bit
• Valid bit tells us..

  whether or not the page is in physical memory if the valid bit is 0 its not present if the valid bit is 1 the page is present.
• Referenced bit tells us...

  indicates whether the page has been accessed recently
• cache control bit tells us...

  whether or not caching is allowed for this page.
• Dirty bit tells us

  indicates whether the page has been modified since it was loaded into memory.