1.1.1 Structure & function of the processor

• Processor architecture

  • Von Neumann: instructions and data are in binary and are stored in the same memory unit. (cheaper and programs can be optimised in size)
  • Harvard: separate memory units for instructions and for data, plus buses to deal with extra section(s) (quicker execution as fetching is parallel but memories can be different sizes too)
  • Contemporary: combination of Harvard and Von Neumann. VM used when working with data and instructions in main memory, Harvard to divide cache into instruction and data cache.
• Von Neumann processor

  • Control unit: manages executions of instructions, manages processor memory and timing via an external clock, controls & coordinates activities of the CPU and stores data back in memory.
  • Memory (RAM): stores parts of the OS currently in use, data and application software in use. 
  • ALU: arithmetic, logic calculations, input & output for processor.
  • An interrupt can occur, where a signal is sent to the processor indicating a process needs attention at the end of every FDE cycle, which the CU checks.
• Buses

  • Buses are specialised for purpose.
  • Control bus: signal sent from CU with either read or write.
  • Address bus: transfers address from MAR to RAM to find said memory location

  Data bus: transfers data held in the memory location
• Control signals can include:

  • Bus request - device requesting use of data bus.
  • Bus grant - shows CPU has granted access to data bus.
  • Memory write - data written to address location using this bus.
  • Memory read - data read from a specific location to be placed onto the data bus.
  • Interrupt request - shows device is requesting access to the CPU.
  • Clock - synchronises operations.
  • Interrupt request - shows device is requesting access to the CPU. See more here.
  • Clock - synchronises operations.
• Registers

  • PC: contains address of the next instruction to be executed.
  • MAR: holds the address of memory that needs to be accessed now.
  • MDR: holds the data read or ready to be written to memory or the instruction just read from memory.
  • CIR: holds a copy of the instruction being executed.
  • ACC: holds results of calculations performed by ALU as well as temporary storage of long calculations. 
• Recall the Fetch-decode-execute cycle.


  Here it is:

  
• Execute examples:

  • LDA 5: 5 is copied into MAR, MAR is copied via address bus to memory, read signal is sent on a control bus, data at that memory location is copied via data bus to MDR and MDR is copied to ACC.
  • STA 8: ACC is copied to MDR, the address (8) is copied to MAR, write signal is on the control bus and MAR is copied via address bus to memory, accumulator is copied to MDR so that it can be stored into the memory location of 8, via the data bus. 
• Branching

  • BRP: branch if positive
  • BRA: branch always
  • BRZ: branch if zero
• Pipelining


  The next instruction can be fetched while, at the same time, the processor is performing arithmetic or logic operations in the ALU for a previous instruction
• Pipelining


  • Allows us to use various registers efficiently, allowing different parts of instructions across multiple stages to be held in different registers at the same time
• Instruction pipeline


  The various stages an instruction must move through the processor
• Arithmetic pipeline


  The parts of an arithmetic operation that can be broken down and overlapped as they are carried out
• Pipelining is not as useful for code which has a lot of branch instructions, as we will need to flush the pipe
• Pipelining is the process of completing the fetch, decode, and execute cycles of three separate instructions simultaneously, holding appropriate data in a buffer in close proximity to the CPU until it’s required. While one instruction is being executed, another can be decoded and another fetched.