Chapter 4

• Von Neumann architecture


  A design architecture for an electronic digital computer with subdivisions of a central arithmetic part, a central control part, a memory to store both data and instructions, external storage, and input and output mechanisms
• The Von Neumann architecture uses a single processor which follows a linear sequence of fetch-decode-execute
• Special registers in the Von Neumann architecture

  • Program Counter (PC)
  • Current Instruction Register (CIR)
  • Memory Address Register (MAR)
  • Memory Data Register (MDR)
  • Status Register
  • Index Register (IX)
  • Accumulator
• Program Counter (PC)


  Keeps track of where to find the next instruction so that a copy of the instruction can be placed in the current instruction register
• Current Instruction Register (CIR)


  Holds the instruction that is to be executed
• Memory Address Register (MAR)


  Used to hold the memory address that contains either the next piece of data or an instruction that is to be used
• Memory Data Register (MDR)


  Acts like a buffer and holds anything that is copied from the memory ready for the processor to use it
• Index Register (IX)


  A microprocessor register used for modifying operand addresses during the run of a program, typically for doing vector/array operations
• Status Register


  Holds results of comparisons to decide later for action, interim results of arithmetic performed, and any errors occurred during the arithmetic operations, like overflow etc.
• Arithmetic Logic Unit (ALU)


  • Where data is processed, involving arithmetic and logical operations
• Assembly code instructions that would use the ALU


  • ADD
  • SUB
  • AND
  • OR
  • XOR
• Control Unit


  Fetches instructions from memory, decodes them and synchronizes the operations before sending signals to other parts of the computer
• Processor clock


  A timing device connected to the processor that synchronizes when the fetch, decode execute cycle runs
• Clock speed


  The number of cycles that are performed by the CPU per second
• Types of buses


  • Control bus
  • Address bus
  • Data bus
• Control bus


  Used by the control unit to communicate and transfer signals to and from the internal and external devices of the system
• The fetch-execute cycle


  1. Fetch a program instruction from memory

  2. Determine what the instruction wants to do

  3. Execute those actions
• Address bus


  Used to carry the address from where data needs to be fetched or placed in main memory
• The fetch-execute cycle


  • Repeated continuously by the CPU from boot up to shut down
  • Completed billions of times per second in modern computers
  • Without it, nothing would be able to be calculated
• Data bus


  A bi-directional bus to access data to and from memory address mentioned in MAR
• Registers involved in the fetch-execute cycle

  • Program Counter (PC)
  • Memory Address Register (MAR)
  • Memory Data Register (MDR)
  • Current Instruction Register (CIR)
  • Control Unit (CU)
  • Arithmetic Logic Unit (ALU)

  
• Ways to increase computer performance

  • Increasing the clock speed
  • Adjusting word length
  • Increasing bus widths
• Program Counter (PC)


  An incrementing counter that keeps track of the memory address of which instruction is to be executed next
• Increasing clock speed generates more heat which can cause processors to burn out
• Memory Address Register (MAR)


  The address in main memory that is currently being read or written
• Peripherals


  Input/output devices used by the system to get information in and out, as they are not internal but are connected to the CPU
• Memory Data Register (MDR)


  A two-way register that holds data fetched from memory (and data ready for the CPU to process) or data waiting to be stored in memory

  
• Types of peripherals


  • Input devices
  • Output devices
• Current Instruction Register (CIR)

  A temporary buffer for the instruction that has just been fetched from memory
• Control Unit (CU)


  Decodes the program instruction in the CIR, selecting machine resources such as a data source register and a particular arithmetic operation, and coordinates activation of those resources

  
• I/O controllers


  Electronic circuits that connect to a system bus and an I/O device, providing the correct voltages and currents
• Arithmetic Logic Unit (ALU)


  Performs mathematical and logical operations
• I/O port


  A complementary method of performing input/output between the CPU and peripheral devices in a computer
• Register transfer notation


  1. [PC] -> MAR

  2. (Increment PC)

  3. [MAR] -> MBR

  4. MBR -> CIR

  5. Decode and execute
• Detailed description of Fetch-Decode-Execute Cycle

  1. Load PC into MAR

  2. Fetch instruction from memory to MDR

  3. Load CIR from MDR

  4. Decode and execute instruction
• Interrupt


  A signal to the processor emitted by hardware or software indicating an event that needs immediate attention
• How Interrupts work


  1. Instruction fetched

  2. Current instruction executed

  3. Interrupt presence checked in queue

  4. If interrupt priority is high, save current program data to stack and load interrupt handler

  5. Serve the interrupt

  6. Load data back from stack

  7. Resume previous program
• When an interrupt is generated during a fetch-execute cycle, the CPU copies all register values to a 'stack' in primary memory, executes the interrupt service routine, then loads the original register values back from the stack to continue what it was doing before the interrupt
• Instruction set


  The range of instructions that a CPU can execute
• Examples of instructions


  • LDD
  • ADD
  • STO