HDL

• created verilog


  Philip Moorby by Gateway Design Automation during 1984
• verilog merge with?


  CAdence
• verilog is an IEEE standard what

  1364-1995/ 2001/ 2005
• it is an analog and mixed signal extension


  verilog- AMS
• What is VHDL

  Very high speed integerated circuit hardware description language
• V in VHDL


  very high speed integrated circuit
• VHDL is developed by?

  DOD from 1983 based on ADA language
• VHDL IEEE standard?

  1076-1987/ 1993/ 2002/ 2008
• digital System design model

  Behavioral model, structural, RTL
• describes i/o responses and behaior ng design

  behavioral model
• data flow description


  RTL
• structural model


  components and their interconnection
• 2 document digital system

  Simulation, synthesis
• to verify circuit/system design

  simulation
• circuits from hdl model


  synthesis
• basic verilog building block


  module
• logic function for OR


  " | "
• logic function for AND


  "&"
• Logic funtion for XOR


  " ^ "
• it is the space, tab, and new line

  white space
• format for comments


  //, /*, /*-*/
• CAse sensitivity

  VHDL not case sensitive, verilog case sensitive
• statement delimiters

  semicolon
• list separator


  Commas
• module input, output, or both

  ports
• connect components and are continously assigned values

  Nets
• main type of net

  wire
• store values between assignments

  variable
• main type of variable

  reg
• single bit, or single value

  scalar
• set of values of a given type

  vector
• logic values 0,1,x,z


  0= false,1= true, x= undefine, z= tristate
• HDLs are used in several significant steps in the design flow of an integrated circuit:

  Design entry, logic simulation, logic synthesis, timing verification, fault simulation
• creates an HDL-based description of the functionality to be implemented

  in hardware.

  Design entry
• displays the behavior of a digital system through the use of a computer.

  Logic simulation
• is the process of deriving a list of physical components and their

  interconnections (called a netlist) from the digital system model described in an HDL.

  Logic synthesis
• confirms that the fabricated integrated circuit will operate at a

  specified speed.

  Timing verification
• compares an ideal circuit’s behavior with a circuit

  that contains a process-induced flaw.

  fault simulation