INTRODUCTION

• A hardware description language (HDL) is a computer-based language that describes the

  hardware of digital systems in a textual form.
• HDLs are used in several significant steps in the design flow of an integrated circuit:

  • Design entry
  • Logic simulation
  • Logic synthesis
  • Timing verification
  • Fault simulation
• Design entry creates an HDL-based description of the functionality to be implemented

  in hardware.
• Logic simulation displays the behavior of a digital system through the use of a computer.
• Logic synthesis is the process of deriving a list of physical components and their

  interconnections (called a netlist) from the digital system model described in an HDL.
• Timing verification confirms that the fabricated integrated circuit will operate at a

  specified speed.
• fault simulation compares an ideal circuit’s behavior with a circuit

  that contains a process-induced flaw.
• VHDL is a Department of Defense–mandated language.
• Verilog began as a proprietary HDL of Cadence Design Systems, but Cadence transferred

  control of Verilog to a consortium of companies and universities known as Open Verilog

  International (OVI) as a step leading to its adoption as an IEEE standard.
• Keywords

  • predefined lowercase identifiers that define the language constructs (e.g., module, endmodule,

  input, output, wire, and, or, and not).
• module refers to the text enclosed by the keyword pair module . . . endmodule.
• identifiers are names given to modules, variables (e.g., a signal), and other elements of the

  language so that they can be referenced in the design.
• Identifiers must start with an alphabetic character or an underscore, but they cannot start

  with a number.
• The port list of a module is the interface between the module and its environment.
• Internal connections are declared as wires.
• An HDL description that provides the stimulus to a design is called a test bench.
• The initial statements are commonly used to describe waveforms in a test bench. The set of

  statements to be executed is called a block statement and consists of several statements

  enclosed by the keywords begin and end.
• User-Defined Primitives

  • The logic gates used in Verilog descriptions with keywords and, or, etc., are defined by the system

  and are referred to as system primitives.
• The user can create additional primitives by defining them in tabular form. These types of circuits

  are referred to as user-defined primitives (UDPs).

  • One way of specifying a digital circuit in tabular form is by means of a truth table. UDP descriptions

  do not use the keyword pair module . . . endmodule. Instead, they are declared with the

  keyword pair primitive . . . endprimitive.
• • Verilog – created in 1984 by Philip Moorby of Gateway Design

  Automation (merged with Cadence)
• Verilog – created in 1984 by Philip Moorby of Gateway Design

  Automation (merged with Cadence)

  • IEEE Standard 1364-1995/2001/2005
• Verilog-AMS – analog & mixed-signal extensions
• VHDL = VHSIC Hardware Description Language

  (VHSIC = Very High Speed Integrated Circuits) •

  Developed by DOD from 1983 – based on ADA language

  • IEEE Standard 1076-1987/1993/2002/2008

  • VHDL-AMS supports analog & mixed-signal extensions
• HDLs in Digital System Design

  • Model and document digital systems

  • Behavioral model

  • describes I/O responses & behavior of design

  • Register Transfer Level (RTL) model

  • data flow description at the register level

  • Structural model

  • components and their interconnections (netlist)

  • hierarchical designs
• • Simulation to verify circuit/system design

  • Synthesis of circuits from HDL models • using components from

  a technology library
• The module is the basic Verilog building block
• • Identifiers: any sequence of

  • letters (a-z, A-Z), digits (0-9), $ (dollar sign) and _ (underscore).
• Semicolons are statement delimiters; Commas are list separators
• • Nets connect components and are continuously assigned values
• wire is main net type (tri also used, and is identical)
• Variables store values between assignments

  • reg is main variable type
• • Scalar is a single value (usually one bit)

  • Vector is a set of values of a given type