A special register to temporarily store the results of operations performed by the ALU
Address Bus
Carries the memory location address of the register the data is being carried to or from
Arithmetic and Logic Unit (ALU)
A part of the CPU that performs arithmetic calculations and logical operations on data for the computer programs
Bus
A physical set of parallel wires connecting and carrying groups of bits between several components of a computer
Cache
A small and fast but expensive memory in the CPU used to store instructions and data that are accessed regularly
Clock speed
The frequency at which the internal clock generates signals switching between 0 and 1. It controls how often instructions are executed and data is fetched
Contemporary Processor Architecture
A modern computer architecture combining elements of both Von Neumann and Harvard architectures
Control Bus
A bi-directional bus carrying control signals from the Control Unit (CU) to synchronise access and use of data
Control Unit (CU)
A part of the CPU that controls and manages the execution of instructions. It sends control signals to coordinate execution and controls Fetch-Decode-Execute cycles and buses
Current Instruction Register (CIR)
A special register that stores the current instruction being executed and decoded. The instructions are divided into operand and opcode
Data Bus
A bi-directional bus for carrying data and instructions between the processor and memory
Accumulator (ACC)
A special register to temporarily store the results of operations performed by the ALU
Address Bus
Carries the memory location address of the register the data is being carried to or from
Arithmetic and Logic Unit (ALU)
A part of the CPU that performs arithmetic calculations and logical operations on data for the computer programs
Buses
A physical set of parallel wires connecting and carrying groups of bits between several components of a computer
Cache
A small and fast but expensive memory in the CPU used to store instructions and data that are accessed regularly
Clock Speed
The frequency at which the internal clock generates signals switching between 0 and 1. It controls how often instructions are executed and data is fetched
Contemporary Processor Architecture
A modern computer architecture combining elements of both Von Neumann and Harvard architectures
Control Bus
A bi-directional bus carrying control signals from the CU to synchronise access and use of data
Control Unit
A part of the CPU that controls and manages the execution of instructions. It sends control signals to coordinate execution and controls Fetch-Decode-Execute cycles and buses
Current Instruction Register (CIR)
A special register that stores the current instruction being executed and decoded. The instructions are divided into operand and opcode
Data Bus
A bi-directional bus for carrying data and instructions between the processor and memory
Fetch-Decode-Execute Cycles
1. Fetching from memory (supplying the address and retrieving the instruction from memory)
2. Decoding (interpreting the instruction and then reading and retrieving the required data from their addresses)
3. Executing the instruction (CPU carries out the required actions)
Harvard Architecture
A computer architecture that stores data and instructions in separate memories to allow the next instruction to be read while data is currently being read or written
Memory Address Register (MAR)
A special register that stores the memory address of the next instruction to load or data to use
Memory Data Register (MDR)
A special register that temporarily stores data to be read from or written to the computer's memory
Number of Cores
A core is a processing unit that handles instructions with its own fetch-execute-decode cycles. Multi-core processors have multiple cores that can run simultaneously
Pipelining
The simultaneous decoding of several instructions by decoding the next instruction and fetching the one after while the current one is being decoded
Program Counter (PC)
A special purpose register that stores the address of the next instruction to execute
Registers
Special memory cells that can be accessed quickly. They temporarily store data and control information
Von Neumann Architecture
A computer architecture where a single control unit manages program control via a linear sequence of fetch-execute-decode cycles
Complex Instruction Set Computer (CISC)
A more complicated and expensive processor design that can execute a series of tasks in a single complex instruction built into the hardware. The variety of instructions means less RAM is used, but pipelining is not possible
Graphic Processing Unit (GPU)
A specialised processing unit with a huge number of small cores that allow efficient parallel computation for tasks such as computer graphics, machine learning, data mining etc
Multicore Systems
Several CPU cores are incorporated into a single processor chip to help distribute workload
Parallel Processing System
Splitting a job into several subtasks which are simultaneously carried out by each core in the system
Reduced Instruction Set Computer (RISC)
A simpler processor design that can only execute a single simple instruction each clock cycle. This uses more RAM but allows pipelining
Flash Storage
A solid state technology that stores data on a collection of memory chips. No moving parts as data is accessed by software
Input Devices
Peripheral devices that allow the user communicate and to pass readable data into a computer, decode it and send it to the CPU
Magnetic Storage
Relies on the polarisation of magnetic particles to store bits on a magnetic material which is typically moved mechanically. A high capacity and low cost means of storage
Optical Storage
Data is stored in the reflectivity (pits and lands) of a surface, and is read and written to by a laser