1.1 Often forgotten!

• CISC often has:

  • single instruction set
  • each instruction may take multiple cycles
  • instructions have a variable format
  • more instructions available
  • integrated circuits are expensive
  • more complicated design
• RISC often is:

  • instructions perform a single task
  • limited number of instructions available
  • simple processor design, less energy & heat
  • run faster, more simple
  • uses more RAM
• Von Neumann has:

  • single control unit
  • one instruction at a time
  • uses the FDE cycle
  • Program and data stored together in the same format.
• Harvard:

  seperate memory units, for instructions & data, plus buses to deal with the extra sections.
• The CU is responsible for:

  • controlling the processor
  • decoding instructions
  • sending signals to the control bus
• CIR will be sent the opcode and operand from MDR and also hold the new address in the case of a jump.
• MDR acts as a buffer, holds the data referenced by MAR. It will also hold data and instructions fetched from memory. Sends instruction to CIR.
• The accumulator:

  I/O - Gateway/buffer

  Temporary storage - for arithmetic calculations