Silicon Wafers

• Silicon


  One of the most abundant elements on Earth, constituting nearly 28% of Earth's crust. It is a semiconductor that is relatively easy to process and can form an excellent quality oxide, making it ideal for microelectronic applications.
• Most circuits in today's microelectronics are made on silicon substrates

  
• Gallium arsenide (GaAs)


  The second most popular material in microelectronics after silicon
• Silicon crystal structure


  • It has the same structure as diamond, consisting of two interpenetrating face-centred cubic lattices displaced along the body diagonal of the cubic cell by one quarter the length of the diagonal
  • The size of one unit cell or lattice constant a is 0.54306 nm
• Crystal orientation


  Defines the electrical properties of the device, so devices fabricated on wafers with different orientations will exhibit different behaviour even if the material is the same
• Common crystal orientations used in silicon

  • (100)
  • (110)
  • (111)
• Silicon purification


  1. Extracted from silica sand (SiO2)

  2. Reduced to 98% pure metallurgical-grade silicon (MGS) using carbon at high temperature

  3. Impurities removed by converting MGS to gaseous trichlorosilane (SiHCl3) and distilling

  4. SiHCl3 converted back to solid electronic-grade silicon (EGS)
• Czochralski crystal growth


  1. Polycrystalline EGS placed in silica crucible and melted

  2. Single crystalline seed with desired orientation dipped into melt

  3. Seed withdrawn, causing silicon to solidify and acquire seed's orientation

  4. Pulling rate controlled to form thin neck then increase diameter

  5. Magnetic fields applied to improve quality uniformity

  6. Dopants can be incorporated during growth
• Dopant concentration


  Final doping concentration in ingot is usually lower than in melt, depending on segregation coefficient of dopant
• Wafer preparation


  1. Ingot marked for orientation and doping type

  2. Wafers sliced from ingot and polished
• Types of crystal defects

  • Point defects: vacancies, self-interstitials, foreign interstitials, substitutionals
  • Line defects: some types of linear dislocations
  • Area defects: stacking faults, dislocation loops, twinning
  • Volume defects: precipitates
• Wafer engineering techniques


  • Epitaxial wafers: additional Si layers deposited to bury defects from Czochralski process

  Silicon-on-insulator (SOI): devices encased in insulating material to reduce parasitic capacitances and power consumption
• Wafer bonding SOI


  1. Two wafers bonded together, one thinned by polishing and etching

  2. Highly doped epitaxial Si layer on one wafer acts as etch stop

  3. Wafers bonded at high temperature to form Si-O-Si bonds

  
• Smart-cut SOI


  1. Donor wafer oxidised and implanted with hydrogen to create gas bubbles

  2. Wafer bonding at room temperature, then annealing to split donor wafer

  3. Further annealing to strengthen SOI structure

  
• SIMOX SOI


  1. Oxygen implanted into Si wafer, then annealed to form buried oxide

  2. Thickness of Si cap controlled by implantation energy, but results in high defect density