Directs the operations of the CPU, controlling and coordinating its activities, managing the flow of data, accepting the next instruction, decoding instructions, and storing the resulting data back in memory
Registers
Program Counter (PC)
Accumulator (ACC)
Memory Address Register (MAR)
Memory Data Register (MDR)
Current Instruction Register (CIR)
Program Counter (PC)
Holds the address of the next instruction to be executed
Accumulator (ACC)
Stores the results from calculations
Memory Address Register (MAR)
Holds the address of a location that is to be read from or written to
Memory Data Register (MDR)
Temporarily stores data that has been read or data that needs to be written
Current Instruction Register (CIR)
Holds the current instruction being executed, divided up into operand and opcode
Buses
Parallel wires which connect two or more components inside the CPU, including the data bus, control bus, and address bus
Data Bus
Bi-directional bus used for transporting data and instructions between components
Address Bus
Bus used to transmit the memory addresses specifying where data is to be sent to or retrieved from
Control Bus
Bi-directional bus used to transmit control signals between internal and external components, including bus request, bus grant, memory write, memory read, interrupt request, and clock
Assembly Language
Uses mnemonics to represent instructions, with the instruction divided into operand and opcode
Fetch-Decode-Execute Cycle
1. Fetch phase: Address from PC copied to MAR, instruction held at that address copied to MDR, contents of PC increased by 1, value in MDR copied to CIR
2. Decode phase: Contents of CIR split into operand and opcode
3. Execute phase: Decoded instruction executed
Factors affecting CPU performance
Clock speed
Number of cores
Amount and type of cache memory
Clock Speed
Determined by the system clock, which generates signals switching between 0 and 1, with each CPU operation starting as the clock changes from 0 to 1
Number of Cores
Independent processors able to run their own fetch-execute cycle, allowing a computer with multiple cores to complete more than one fetch-execute cycle at a given time
Cache Memory Types
Level 1 Cache (very fast, small capacity)
Level 2 Cache (relatively fast, medium capacity)
Level 3 Cache (larger and slower)
Von Neumann Architecture
Includes basic computer and processor components (control unit, ALU, registers, memory units) with shared memory and data bus for both data and instructions, built on the stored program concept
Harvard Architecture
Has physically separate memories for instructions and data, useful when memories have different characteristics, allowing optimization of memory cell size and bus width
Advantages of Von Neumann Architecture
Cheaper to develop
Programs can be optimised in size
Advantages of Harvard Architecture
Quicker execution
Memories can be different sizes
Contemporary Processors
Use a combination of Harvard and Von Neumann architecture, with Von Neumann for working with data and instructions in main memory, and Harvard for dividing the cache into instruction cache and data cache