DEch6

• Flip-Flops (F/F)
• Topics

  • Introductory Concepts
  • Numbering Systems
  • Boolean Algebra
  • Combinational Logic
  • Flip-Flops – Part 1
  • Arithmetic Circuit
  • Counters & Shift Registers
  • Logic Families
• Flip-Flops (F/F)

  • Introduction
  • Nand / Nor Latch
  • SC F/F
  • JK F/F
  • D F/F , D Latch
  • Asynchronous Control (Clear/Preset)
  • Timing Parameters
  • One-shot Devices
  • Schmmit Trigger Inverters
• Flip Flop (F/F)


  A memory element where the output depends not only on the current inputs but also the previous output
• Combinational circuits are not memory elements because the output depends only on the current inputs
• Typical F/F

  • Normally has 2 outputs designed to be opposite each other under normal working condition
  • Has at least 2 inputs: S (Set) and C (Clear)
• Set the F/F


  Make Q = 1
• Clear the F/F


  Make Q = 0
• NAND Latch

  1. S=0, C=1 - Set the latch

  2. C=0, S=1 - Clear the latch

  3. S=C=1 - No change

  4. S=C=0 - Invalid state
• When the NAND latch moves from invalid state to no change state, the result could be Q=0 or Q=1 due to ambiguity
• We should not let the NAND latch enter the invalid state
• NAND Latch symbol

  Bubbles indicate active LOW inputs
• Given Set and Clear waveforms, obtain the Q waveform of a NAND gate latch


  1. S=1, C=1 - No change

  2. S=1, C=0 - Clear

  3. S=0, C=1 - Set
• Switch contact bounce

  Produces erroneous input to digital circuit
• Using a NAND latch to clear contact bounce


  1. Switch to contact 2

  2. Latch cleans up the transition on VOUT
• SET

  When S=1, C=0, the latch is set and Q=1
• CLEAR


  When S=0, C=1, the latch is cleared and Q=0
• Obtaining Q waveform from SET and CLEAR waveforms


  1. Draw lines through transitions

  2. Determine Q based on SET and CLEAR inputs
• NOR Latch


  • S and C are active HIGH inputs
  • When S or C is '1', they will cause predefined change to the output
• NOR Latch application

  • Detecting interruption of a light beam
  • Alarm sounds until CLEAR switch is activated
• NAND Latch vs NOR Latch

  Differences in truth table and logic gates
• Synchronous Circuits

  Events are synchronised with a clock signal<|>Outputs can only change state when the clock signal makes a transition
• Clock Signal


  Periodic signal, can be rectangular pulses or square pulses<|>Described by duty cycle, period, positive going transition (PGT), negative going transition (NGT)
• Clocked SC Flip-Flop

  • Additional CLK input, output can only change at clock edges
  • Active on PGT or NGT of clock
• Synchronous Control Inputs

  S and C inputs have to work together with the clock
• Obtaining Q waveform from S, C, CLK waveforms


  Determine Q based on S, C inputs and clock edges
• Flip Flops


  49
• Clocked SC Flip-Flop (PGT clock)


  Q<|>S<|>C<|>CLK<|>Q
• Clocked SC Flip-Flop (PGT clock)


  • Q can ONLY change at the PGT of the clock input
  • No bubble at the CLK input shows that the clock input is active on PGT
• Clocked SC Flip-Flop (NGT Clock)


  Q<|>S<|>C<|>CLK<|>Q
• Clocked SC Flip-Flop (NGT Clock)


  • The bubble at the CLK input shows that the clock input is active on NGT
  • The downward arrows show that Q can ONLY change at the NGT of the clock input
• Synchronous Control Inputs

  S & C are called Synchronous Control Inputs, as they have to work together with the CLK
• Given the S,C waveforms, obtain the Q waveform


  1. S=0, C=0, no change

  2. S=1, C=0, set

  3. S=0, C=1, Clear

  4. S=1, C=0, Set
• Given the S,C waveforms, obtain the Q waveform


  • Q can ONLY change (if any) at the PGT
  • First, draw upward arrows on PGT, and lines through them
• Given the S,C waveforms, obtain the Q waveform


  • Q can ONLY change (if any) at the NGT
  • First, draw downward arrows on NGT, and lines through them
• IF S or C also change at NGT, to determine Q, do I take the value of S or C just before or after NGT?
• Setup Time tS

  The minimum time required to setup the synchronous control input before active clock transition
• Hold Time tH

  The minimum time required to hold the synchronous control input after active clock transition
• Failing to comply to the requirement of Setup Time tS and Hold Time tH, Q may not respond as expected
• JK Flip-Flop (PGT)

  J is like Set, K is like Clear<|>Invalid State is replaced by Toggle State