part 2

• Data FF (D FF)


  Q follows D at NGT or PGT
• Obtaining Q waveform from D & CLK waveforms


  1. Draw upward arrows on PGT, and lines through them

  2. Work out the rest yourself
• Implementing D FF using JK FF


  J=D, K=NOT(D), Q=D
• D latch vs D FF

  D latch is transparent when EN=1, D FF changes on clock
• Synchronous Control Inputs

  S and C inputs in the clocked SC Flip Flops<|>J and K inputs in the JK Flip Flops<|>D input in the D Flip Flops<|>Must work together with the clock input to effect a change in the Q outputs
• Synchronous system


  Output can change state only when the clock makes an active transition
• Asynchronous system

  Outputs can change state any time when one or more inputs change
• Asynchronous Control inputs (Preset and Clear)

  Level-triggered, active-LOW<|>When not active, FF operates under the control of J, K and clock (clocked operation)
• Clocked JK FF with Preset & Clear


  1. When Preset & Clear are inactive – FF is in Clocked Operation

  2. When Preset or Clear is active – they override Clocked Operation
• Obtaining Q waveform from input waveforms


  1. Draw downward arrows on NGT, and lines through them

  2. Also lines through transitions of Preset & Clear

  3. Preset active overrides clock, Q=1

  4. Clear active overrides clock, Q=0

  
• Timing Parameters

  Setup Time, tS & Hold Time, tH<|>Propagation Delay, tPLH, & tPHL<|>Maximum Clock Frequency, fMAX<|>Minimum Clock Pulse Width, tW(L) & tW(H)<|>Maximum rise time tR & fall time tF of the CLK<|>Asynchronous Active Pulse Width, tW(Clear) & tW(Preset)
• Setup Time tS & Hold Time tH

  Time required for synchronous control input to be stable before and after clock transition
• Propagation Delay, tPLH & tPHL


  Delay from clock to Q going HIGH and LOW
• Maximum Clock Frequency, fMAX


  Highest frequency that may be applied to the clock input of a FF and still have it triggered reliably
• Clock Pulse Width, tW(L) & tW(H)

  Minimum pulse width of CLK signal for reliable triggering
• Clock Rise Time tR and Fall Time tF

  Maximum rise and fall time of the CLK signal transitions required for reliable triggering
• Asynchronous Active Pulse Width

  Minimum time PRESET or CLEAR input must be active to reliably set or clear the FF
• Typical FF Timing Values (ns)
• Flip-Flop Applications


  • Switch debouncing
  • Detecting an input sequence
  • Data storage & transfer
  • Frequency division / Counting
  • Others
• Sequential circuits


  Circuits in which the outputs follow a predetermined sequence of states
• prior to the active clock transition

  5.11
• Time

  25ns<|>41ns<|>15ns<|>all
• Answer the following questions using the Table in the previous slide
• Flip-Flop Applications


  • Switch debouncing (already covered)
  • Detecting an input sequence
  • Data storage & transfer
  • Frequency division / Counting
  • others
• Most of these applications fall into the category of sequential circuits
• Sequential circuit


  A circuit in which the outputs follow a predetermined sequence of states
• Chp 5 Flip Flops


  42
• Detecting an input sequence (i)


  1. As X become 1 regardless of which input goes HIGH first

  2. How to have X=1 only if A goes HIGH first, and then B goes HIGH some time later ? See next slide for a possible solution.
• The above circuit cannot detect the input sequence
• Chp 5 Flip Flops


  43
• Detecting an input sequence (ii)


  1. A is fed to J, B is fed to CLK. K=0 always. X can only change on PGT of B.

  2. A become '1' before B, therefore, X becomes '1' on PGT of B.

  3. A become '1' after B, therefore, X remains '0' on PGT of B.
• Parallel Data Transfer / Storage


  1. Combinational Logic Circuit outputs X, Y, Z

  2. On NGT, X, Y, Z is transferred to Q
• Frequency Division and counting

  1. A few FF are cascaded, with the CLK connected to the previous Q.

  2. The Clock Pulse is applied to the CLK of the first FF.

  3. All J & K = 1
• B's CLOCK comes from A, i.e. B will toggle at every NGT of A


  With J=K=1, A will toggle at every NGT of the CLOCK
• If the Clock Frequency (fCLK) is given as 16KHz

  T of A is double T of CLK => freq of A is ½ freq of CLK

  Likewise ...
• For N FFs the frequency of the last FF is 1/2N of the CLK frequency
• State Transition Diagram


  Shows the counting sequence
• MOD number

  The number of states the counter goes through in each complete cycle before it RECYLES back to its starting state
• MOD Number

  MOD number = 2N

  N= number of FF
• Flip-Flop Related Devices

  Multivibrators