Internal hardwares

• Device drivers


  software that interacts directly with the I/O controller
• What are the functions of an I/O controller

  • converts the signals recieved from a peripheral device into a format the computer can process and vice versa
  • recieves I/O requests from the CPU and then sends device-specific control signals to the device its is controlling
  • manages the data flow to and from the device freeing the CPU to get on with other tasks
• Control Bus


  used to send control signals between the I/O controller and the processor and memory
• Control signals include


  Memory write

  Memory read

  Bus request

  Bus grant

  clock
• Memory read


  causes data from the addressed location to be place on the data bus
• Memory write


  causes data on the data bus to be written into an addressed location
• Bus request


  indicates that a device is requesting use of the data bus
• Bus grant


  indicates that the CPU has granted access to the data bus
• What is a Clock and what is it measured in?

  • The electronic unit that synchronises related components by generating pulses at a constant rate
  • measured in hertz
  • the higher the clock rate, the faster the computer might work
• What is a Data bus

  • Sends data between CPU components and is bi-driectional so data can be sent both ways
• Address bus

  • a bus that sends memory addresses from the processor to CPU components.
  • the address may be for the next instruction to be process or data refered to in the instruction
• stored program concept

  machine code instructions are loaded into main memory to be executed by the processor

  the instructions are fetched one at a time and executed immediately by the processor in a sequential order
• Harvard Architecture


  • seperates the data and instructions into seperate memories - Each using their own buses
  • Reading and writing can be done at the same time as fetching an instruction
  • used by risc processors
• Von neuman architecture

  • Shared memory space for instructions and data
  • Instructions and data are in the same format
  • A single control unit or processor follows a linear fetch, decode, execute cycle
  • Registers are used as a fast access to instructions and data
• Words (computer)

  memory is divided up in equal units called words

  each word has a seperate memory address

  word length is usualy 8,16,32
• Instruction sets

  is a set of commands that a microprocessor can understand and execute and they are specific to the processor
• What does an instruction contain?

  An opcode and operand
• Operand

  the part of a computer instruction that specifies what data is to be manipulated or operated on
• immediate addressing

  the operand is the datum (the value in the address part is the actual value being used not the location of the value)
• direct addressing

  the operand is the address of the datum ( the address in memory is where the value actually is that should be used)
• ISR Effect on Fetch-Execute Cycle

  Suspends current instruction, pops PC, executes ISR, and resumes execution.
• Interrupt

  A signal sent to the CPU to stop its current activity and attend to a higher-priority task.
• Control unit


  • coordinates all activites of the CPU
  • directs the flow of data between the CPU and other devices
  • Sends memory read and write requests as well as other commands and control signals through the control bus
  • Makes extensive use of the status register and clock
• Status register

  • contains information about the state of the processor
  • individual bits are implicitly or explicitly read and/or written by the machine code instructions executing on the proccessor
  • these bits are set on or off and can be checked at any point
• Program counter register


  • Holds the address of the next instruction to be executed
  • this could be the next instruction in a sequence of instructions
  • has a very close relationship with the memory address register
  • at the start of every new FDE cycle the address held in the PC is copied to the MAR
• Memory Address register


  • Holds the address of the memory data of which data or instruction is to be fetched or to which data is written
  • Sends these address to memory down the address bus
• Memory buffer register

  • Use to temporaily store the data which is read from or written to memory
  • All data to and from memory must travel down the data bus and pass through the MBR
• Current instruction register

  Holds the current instruction being executed

  Contents of MBR are copied to CIR

  Contains the operator and operands of the current instruction
• What components effect the proccessor speed?

  • Clock Speed
  • Cache memory
  • Multiples copies of the CPU
  • Width of Data bus
  • Widh of memory bus
• How does clock speed effect the proccessor speed?


  The higher the clock speed, the more pulses are sent more second so more instruction can be executed. A problem with this is that the quicker it is, the more heat generated which can reduce the life-span of the CPU
• How does cache effect the proccessor speed?

  • A small piece of fast memory
  • Used to store frequently used information and reduces time wasted in fetching the same information from main memory time and time again
• How does word length affect the proccessor speed?


  • A word is a group of bits that is treated as a single unit by a processor
  • Higher word lengths allow for more bits to be transferred and manipulated as a single unit
• How does the address bus width affect the proccessor speed?

  • The width of a bus relates to the number of parallel wires that make up the bus
  • Increasing the width of the address bus increases the range of addresses that it can specify
  • Increasing the width of the address bus increases the computer’s amount of addressable memory
  • Adding a single wire doubles the number of addressable memory locations
• How does the data bus width affect the processor speed?


  • Increasing the width of the data bus increases the volume of data that can be transferred over the bus at any one time
  • A wider data bus allows the processor to fetch more data from main memory in one cycle of the fetch-execute cycle
  • This reduces the number of cycles required to fetch large volumes of data
• Steps of the a FDE cycle:

  Step 1: Contents of the program counter are copied into the Memory address register

  Step 2: The contents of the program counter is incremented by 1

  Step 3: The contents of the addressed memory location is loaded into the MBR from main memory

  step 4: The contents in MBR is transfered the the current instruction register

  Step 5: The contents are decoded by the decode unit
• Fetch stage 1:

  • Contents of the program counter are copied into the Memory address register and travels along the address bus to main memory
  • The contents of the program counter is incremented by 1
  • The contents of the addressed memory location is loaded into the MBR from main memory via data bus
  • The contents in MBR is transfered the the current instruction register
• Decode stage 2:

  • Instructions to decode are held in CIR
  • Instructions are decoded by the control unit and split into opcode and operand
• execute stage 3:

  • The opcode identifies the type or operation to be formed by the control unit or it could be the ALU performing calculations and comparisions
  • the status register is updated.if a branch is required the PC is updated and the control bus transfers signals to other components to initiate actions
• Describe what an interrupt is and explain its purpose

  A signal/request sent to the processor so that a device that needs immediate attention of the processor can be dealt with so that the urgent error condtion can be dealt with
• What is an interrupt in computing?


  An interrupt is a signal sent to the processor by another part of the computer requesting the attention of the processor.