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Computer science OCR A Level
1.1.1 Structure and Function of the processor
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Aanya Sinha
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Cards (39)
What is the role of the processor in a computer?
It executes
instructions
for programs
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What does the Arithmetic and Logic Unit (ALU) do?
It completes
arithmetical
and logical operations
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What types of operations does the ALU perform?
Arithmetical
and
logical
operations
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What is the function of the Control Unit?
It directs operations of the
CPU
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What are the jobs of the Control Unit?
Control and coordinate
CPU
activities
Manage data flow between CPU and devices
Accept the next instruction
Decode
instructions
Store resulting data back in memory
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What are registers in a CPU?
Small
memory cells
operating at high speed
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What operations occur in registers?
Arithmetic
,
logical
, and
shift
operations
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What is the purpose of the Program Counter (PC)?
Holds the address of the next
instruction
to execute
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What does the Accumulator (ACC) do?
Stores results from
calculations
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What is the function of the Memory Address Register (MAR)?
Holds the address of a location to
read/write
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What does the Memory Data Register (MDR) temporarily store?
Data that has been
read
or needs to be
written
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What is the role of the Current Instruction Register (CIR)?
Holds the current
instruction
being executed
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What are buses in a CPU?
Parallel
wires connecting CPU
components
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What are the three types of buses in a CPU?
Data bus
Control bus
Address bus
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What does the width of a bus indicate?
Number of
parallel
wires it has
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How does bus width affect data transfer?
It is proportional to
bits
transferred
simultaneously
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What is the function of the Data Bus?
Transport data and instructions between
components
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What is the purpose of the Address Bus?
Transmit
memory addresses
for data retrieval
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What does the Control Bus do?
Transmits control signals between
components
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What are some control signals transmitted by the Control Bus?
Bus request
Bus grant
Memory write
Memory read
Interrupt request
Clock
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What does assembly code use to represent instructions?
Mnemonics
to simplify
machine code
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How is an instruction divided in the Current Instruction Register?
Into operand and
opcode
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What is pipelining in CPU processing?
Completing
fetch
,
decode
,
execute
cycles simultaneously
Holds data in a
buffer
near
the CPU
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What are the two types of pipelining?
Instruction pipelining
and
arithmetic pipelining
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What is the fetch-decode-execute cycle?
Sequence of operations to execute an
instruction
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What happens during the fetch phase?
Address from
PC
copied to
MAR
Instruction copied to
MDR
by
data bus
PC contents increased by 1
MDR value copied to
CIR
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What occurs during the decode phase?
Contents of
CIR
split into operand and
opcode
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What happens during the execute phase?
The
decoded instruction
is executed
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What are the factors affecting CPU performance?
Clock speed
Number of
cores
Amount and type of
cache memory
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What determines the clock speed of a CPU?
The
system clock
generates switching signals
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What is a core in a CPU?
An independent processor running its own
cycle
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How does having multiple cores affect CPU performance?
It allows multiple
fetch-execute cycles
simultaneously
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What is cache memory?
CPU's onboard memory
Stores instructions fetched from main memory
Allows quicker access to frequently used instructions
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What are the types of cache memory?
Level 1 Cache
: Very fast, small capacity (2-64KB)
Level 2 Cache
: Relatively fast, medium capacity (256KB-2MB)
Level 3 Cache
: Much larger, slower memory cell
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What is Von Neumann Architecture?
Basic components of computer and
processor
Shared memory
and data bus for data and instructions
Built on the stored program concept
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What is Harvard Architecture?
Physically separate memories for
instructions
and data
Useful for
embedded processors
Allows
optimization
of memory characteristics
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What are the advantages of Von Neumann Architecture?
Cheaper to develop
Easier
control unit
design
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What are the advantages of Harvard Architecture?
Quicker
execution
of
instructions
Optimized memory sizes
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How do contemporary processors utilize both architectures?
Use
Von Neumann
for main memory
Use
Harvard
for cache division
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