1.1.1

• The CPU stores different components and those components are Control Unit, buses, Arithmetic Logic Unit and registers
• The control unit controls and coordinates the activities of the CPU, directing the flow of data between the CPU and other devices. It accepts the next instruction, decodes it into several steps, and manages its execution and stores the resulting data in memory or registers
• A bus is a communication system that transfers data between components inside a computer. Buses in a computer consist of a series of connectors that transfer signals between internal components. This typically consists of 8, 16, 32, or 64 lines
• The control bus is a bi-directional bus meaning that signals can be carried in both directions. The purpose of the control bus is to transmit command, timing, and specific status information between system components
• Control lines for buses include Bus Request (a device is requesting the use of the data bus), Bus Grant (the CPU has granted access to the data bus), Memory Write (causes data on the data bus to be written into the addressed location), Memory Read (causes data from the addressed location to be placed on the data bus) and Clock (used to synchronise questions)
• The data bus typically consists of 8, 16, 32, or 64 separate lines that provide a bi-directional path for moving data and instructions between system components
• Memory is divided up internally into units called words. A word is a fixed-size group of digits typically 16, 32, or 64 bits, which is handled as a unit by the processor
• The address bus transmits the memory addresses of words that are used as operands in program instructions so that the data can be retrieved and sent back to the processor
• ALU performs arithmetic and logical operations on the data. It can perform instructions such as ADD, SUBTRACT, MULTIPLY, and DIVIDE on float or whole numbers. It can also perform shift operations like shifting bits to the left or right with a register. It can carry out Boolean logic operations using operators like AND, OR, NOT, XOR
• Registers are special memory cells that operate at a very high speed as there are typically 16 general purpose registers in the CPU
• The accumulator will temporarily store all the operations and calculations from the ALU
• The Program Counter (PC) holds the address of the next instruction to be executed that is copied from the Current Instruction Register to the PC
• The Current Instruction Register (CIR) holds the current instruction being executed, divided into operand and opcode
• The Memory Address Register (MAR) holds the address of the memory location from which data or an instruction is to be fetched or to which data is to be written
• The Memory Data Register (MDR) is used to temporarily store the data read from or written to memory. It is sometimes known as the Memory Buffer Register
• In the fetch phase of the fetch-decode-execute cycle is that the address of the next instruction is copied from the program counter (PC) to the memory address register (MAR). Then, the instruction is held at that address and is copied to the memory data register (MDR). Simultaneously, the content of the PC is incremented so that it holds the address of the next instruction. Finally, the contents of the MDR are copied to the current instruction register (CIR)
• In the decode phase, the instruction held in the CIR is decoded. The instruction is split into opcode and operand and the opcode is used to determine the type of instruction and what hardware to use to execute it. The operand holds either the address of the data to be used with the operation, which is then copied to the MAR or the actual data to be operated on, which will be copied to the MDR. Next, the data to be operated on may be passed to the ALU or the Accumulator.
• Lastly in the Execute phase, the appropriate instruction/opcode is carried out on the operand.
• The factors that affect CPU performance are cores, clock speed, cache size and word size
• Clock Speed - The clock is an electrical oscillator that produces a signal to synchronise the operation of the processor. The greater the clock speed the faster the instructions are carried out Clock speed is usually measured in GHz and the number of FDE cycles per second
• A cache is a fast, relatively small capacity set of locations that store frequently used instructions and data.
• Level 1 cache is the smallest and fastest cache.
• Level 2 cache is often shared by cores, slower than L1 cache, and tends to be larger.
• Level 3 cache is slower than L2 cache but larger, and it sits on the processor or near it on the motherboard.
• Storing instructions in a cache reduces the time it takes to access and pass them to a CPU core.
• Cores - the more cores a computer has, the more instructions it can execute at the same time. As a result, the computer will perform more efficiently than computers with the same type of processor but fewer cores. Cores undergo ‘parallel processing’. However, the software may not always be able to take full advantage of all four processors
• In systems designed for parallel processing, each core can work concurrently on different parts of the same task. Since instructions are processed sequentially, this is not always possible.
• The use of pipelining in a processor to improve efficiency. While one instruction is being executed, the next instruction will be decoded and the following instruction will be fetched. Without pipelining, the steps in the FDE cycle take place one after the other. 

  Pipelining reduces latency, the CPU is not idle while waiting for the next instruction which increases the speed of execution, the next instruction is fetched while the current one is decoded/executed and all parts of the processor can be used at any instance in time.
• Word size is the width or length of the address bus and is the number of bits in each of the registers in the processor
• Pipelining processing is divided into instruction pipelining and arithmetic pipeline.
• Flushing the pipe is when you have branching instructions but you need to remove any unnecessary instructions and jump to fetching the needed instruction.
• The advantages of pipelining are:

  Increases the number of instructions executed simultaneously, the CPU does not remain idle and all parts of the processor can be used at any instance in time
• The disadvantages of pipelining are that if there is branch instructions then all of the instructions have to be flushed.
• Von Neumann Architecture is when instructions and data are stored in a common main memory and transferred using a single shared bus
• Harvard architecture separates the data and instructions into separate memories using different buses. Program instructions are no longer competing for the same bus
• The uses of the Harvard architecture are different sized memories and word lengths can be used for data and instructions. Harvard principles are used with specialist embedded systems and digital signal processing (DSP), where speed takes priority over the complexities of design
• The advantages of the Von Neumann architecture are Control unit retrieves data and instructions in the same manner from one memory. Design and development of the Control Unit is simplified, cheaper and faster. Data from input/ output devices and from memory are retrieved in the same manner. Organisation of memory is done by programmers which allows them to utilise the memory’s whole capacity
• The disadvantages of Von Neumann Architecture are parallel implementation of the program is not allowed due to sequential instruction processing. Von Neumann bottleneck are instructions that can only be carried out one at a time and sequentially. Risk of an instruction being rewritten due to an error in the program.
• The advantages of the Harvard Architecture are due to instructions and data being transferred in different buses, this means there is a smaller chance of data corruption, Harvard architecture offers a high performance, as this architecture allows a simultaneous flow of data and instructions. These are kept in a separate memory and travel via separate buses.
• The disadvantages of Harvard architecture are the memory dedicated to each (data and instructions) must be balanced by the manufacturers. This is because if there is free memory data, it cannot be used for instructions.