CPU Structure

• The control unit of the CPU is responsible for organising the sequence in which instructions are executed

  The control unit also decodes the instructions. This means their opcode and operand are analysed to determine what needs to be done to execute the instruction

  Finally, it controls the other components of the CPU
• The control unit is responsible for the following tasks:

  • It uses control signals to enable data to be read and written to main memory
  • It decodes every instruction that the processor will execute, as well as determining what needs to be done to execute it
  • It decides the sequence of micro-operations that need to be performed to carry out the instruction
• The control unit uses control lines to ensure that only one component is using each bus at any given time
• Bus request - Component wants to use the data bus
• Bus Grant - Issues the authority for the device to use the bus
• Memory Write - Causes data in the data bus to be written to the address in the memory bus
• Memory Read - Reads the content from the memory bus
• • Clock - Sends regular electronic pulses to synchronize components
• The Arithmetic Logic Unit (ALU) is responsible for performing mathematical calculations such as:

  • Addition and Subtraction
  • Boolean operations
  • Comparisons between values
  • Shifting binary patterns
• The clock generates regular clock pulses by emitting a signal that continuously oscillates between a low (or 0 ) and a high (or 1 ) state. The clock signal is used to synchronize the operations of the processor components.
• A rising edge is a change from a low (or 0 ) state to a high (or 1) state. The opposite is called a falling edge . The time taken between two sequential rising edges is called the clock period and it corresponds to one clock cycle.
• Every operation requires a number of clock cycles to complete; the number of cycles is specific to each type of processor. Fetching data may require several cycles, although it is referred to as one operation
• Registers are temporary stores usually integrated into the CPU and hold intermediate values
• The first register is called the Program Counter (PC)

  This holds the address of the next instruction to be executed

  It can also hold the address to the jump to if required

  At the start of every f-d-e cycle, the address in the PC is written to the MAR
• The Memory Address Register (MAR) holds the memory address from which data or instructions is to be fetched or which data is to be written

  It uses the address bus to send such addresses down to memory
• The Memory Data Register (MDR) is used to temporarily store the data that is read from or written to memory.

  All data to and from memory must travel down the data bus and pass through this register which is why it is called the gateway to the processor
• The Current Instruction Register (CIR) holds the instruction currently being executed by the CPU

  The contents of an MDR are copied to this register

  It contains the opcode and operand of the instruction
• The Accumulator is a type of general-purpose register.

  Data or control information is stored within it

  It stores temporary data while instructions are being executed and/or calculations are being carried out

  It enhances the performance of the CPU, as more general-purpose registers are more useful

  It temporarily stores the calculations of the ALU
• There are three main types of busses:

  • Data Bus
  • Address Bus
  • Memory Bus
• The address bus carries memory addresses that identify where the data is being read from or to
• The data bus carries the binary 1s and 0s that make up the actualt information being transmitted by the CPU
• The control bus carries command and control signals to and from every other component in the CPU
• At a low level, computers use assembly code as it has a direct relationship with the CPU

  Assembly code uses mnemonics
• There are some main mnemonics that are needed:

  • ADD --> addition
  • SUB --> subtractionb
  • STA --> store
  • LDA --> load
  • BRA --> Branch Always
  • BRZ --> Branch if Zero
  • BRP --> Branch if positive
  • INP --> Input
  • OUT --> Output
  • HLT --> End program
  • DAT --> Data location
• A CPU uses the Fetch Decode Execute cycle to carry out instructions
• Fetch stage:

  • The PC register is checked, to see the address of the next instruction to be executed
  • The address is then stored and copied into the MAR register
  • The address is sent along the address bus into main memory where it waits to recieve a signal from a control bus
  • The control unit sends a read signal along the control bus to main memory
  • The contents stored at the memory address are then sent along the data bus to the MDR register
• Decode Stage:

  • The instruction in the CIR is decoded by the decode unit of the CU
  • The instruction is made of opcode which is what to do in the instruction
  • It is also made of operand which is what to do the instruction to
  • Operand could contain the actual data or an address
• Execute Stage:

  • The address in the operand is sent to the MAR register
  • The address is sent down the address bus to main memory
  • the control unit sends a read signal along the control bus to main memory, to read the data stored in memory
  • The contents are then stored in the MDR via the data bus
  • The contents of the MDR register are copied to the accumulator
• We can also branch out from instructions

  The opcode can be analysed, and its command can be identified

  if the command is a branch, then it replaces the value held in the PC with the contents of the operand from the CIR

  Now, as the PC's contents have been updated to a new memory location, it means that the program can jump around the memory
• Clock speed is measured in hertz

  It refers to the number of instruction cycles executed by the CPU per second

  Modern processors operate at Gigahertz - billions of cyclers per second

  A faster clock speed enhances CPU performance as more cycles are carried per second so more instructions are carried out quickly
• Cache is a temporary store of frequently used data and instructions, integrated onto the CPU, to store them in low latency to the CPU

  It is much quicker to access than RAM. However, small amounts are only required, so as to achieve minimal latency and to minimize cost

  A larger cache size enhances CPU performance, as more frequently used data and instructions can be stored in low latency to the CPU, so instructions can be executed more quickly
• A CPU core is an individual CPU in itself

  For example a quad-core processor has 4 CPUs, each with their own ALUs, registers, etc

  As a result, more cores give the processor to run multiple programs simultaneously

  However, cores have to communicate with each other, and many programs aren't designed to make maximum use of multiple cores.

  Therefore, it can be a grey area
• INP instructions let a user input some data into the accumulator

  An address is not to be put before them
• OUT instructions output the data in the accumulator

  An address is not to be put before them
• STA instructions store given data in a memory address

  We do put an instruction before them

  Eg:

  INP

  STA x

  This stores inputted data in the memory address " x "
• LDA → Load the accumulator with the memory address specifies (You DO put an address location after it)

  EG:

  INP

  STA x

  LDA x

  This inputs data from the user, stores it in the address x and loads this data into the accumulator
• BRA → Use the memory address specified as the address of the next instruction (You DO put an address location after it - jump to the address specified)

  EG:

  INP

  STA x

  BRA Label1

  Label1 OUT

  Label1 is essentially a subroutine - it is used with branches, as it can tell branches to execute certain lines of code
• BRP → Use the memory address specified as the address of the next instruction if the contents of the Accumulator is a positive number (You DO put an address location after it - jump to the address specified)

  EG:

  INP

  STA x

  LDA x

  INP

  STA y

  SUB y

  BRP Label1

  Label1: OUT

  This program inputs two variables, x and y, subtracts them, and if the answer is positive, it outputs the subtraction result
• BRZ - Use the memory address specified as the address of the next instruction if the contents of the Accumulator is 0 You DO put an address location after it - jump to the address specified)

  EG:

  INP

  STA x

  LDA x

  INP

  STA y

  SUB y

  BRZ Label1

  Label1: OUT

  The above program takes two variables, and outputs 0 if they are equal, as x-y = 0
• BIOS stands for basic input output system