1.1.1 Structure and function of the processor

Cards (114)

  • Control Unit(CU)
    1. Sends out control signals to other parts of the CPU, e.g. read or write signals to memory.
    2. Executes programs by following the fetch-decode-execute cycle.
    3. Contains the clock,which coordinates CPU activity,and the decoder
  • Arthmetic Logic Unit (ALU)
    1. Carries out calculations and logical operations upon the data.
    2. All the usual Add,Multiply,Divide and Subtact calculations will be available but also data comparisons such as "Greater Than" , "Less Than" and "Equal To".
  • Program Counter (PC)

    Holds the address in memory of the next instruction and holds the location of the next instruction
  • Memory Address Register (MAR)
    Stores the address of the data that has to be fetched from or sent to memory
  • Memory Data Register (MDR)

    Stores the data that has been fetched from or is about to be stored in memory
  • Current Instruction Register (CIR)
    Stores the most recently fetched instruction,waiting to be decoded and executed
  • Accumulator (ACC)
    Holds the results of calculations and operations performed by the ALU
  • Address Bus
    Provides a memory address to the system memory or input/output devices
  • Data Bus

    Transfers data between the CPU and memory or Input or Output devices and vice versa
  • Control Bus
    Provides control signals that cause the memory or Input or Output to perform a read or write operation
  • What is the task of the CPU
    The task of the CPU is to execute programs by repeatedly carrying out the fetch-decode-execute cycle
  • Fetch-Decode-Execute Cycle-Fetch: 1-3
    1. The program Counter copies the address of the next instruction it contains into the Memory Address Register (MAR).
    2. The Control Unit loads the address to be used on the Address Bus.
    3. The Control Unit triggers a read signal down the Control Bus that causes main memory (RAM) to place the instruction being asked for on to the Data Bus.
  • Fetch-Decode-Execute Cycle- Fetch 4-6:
    4. The instruction on the Data Bus is loaded into the Memory Data Register.
    5. The Memory Data Register copies the instruction into the Current Instruction Register (CIR). 6. The Program Counter can now be increamented by one to point to the next instruction
  • Fetch-Decode-Execute Cycle-Decode:
    1. The Contents of CIR are sent to the Control Unit.
    2. The Control Unit then decodes the instruction
  • During the execution phase of the Fetch-Decode-Execute Cycle:
    • The instruction within the Current Instruction Register (CIR) is carried out by the CPU
  • Different ways the register can be changed during execution phase, depending on the instruction:
    • If a memory location is to be read from or written to (LDA or STA), the address stored within the CIR will be loaded into the Memory Address Register (MAR)
    • For STA instruction, the data stored in the Accumulator (ACC) is sent to memory
    • For LDA instruction, the data is loaded from memory into the ACC
  • For calculations (ADD or SUB) during execution phase:
    • The content of the Memory Data Register (MDR) and ACC are sent to the Arithmetic Logic Unit (ALU)
    • The result is sent back to the ACC
  • Clock speed
    A clock in the control unit sends a pulse at fixed intervals to controls the speed that the CPU carries out the Fetch-Decode-Execute Cycle
  • Overclocking:
    Some CPUS allow the clock speed to be altered this causes faster performance but generates more heat and could damge the CPU
  • Cache
    Cache is a small amount of very fast memory bulit into the CPU.Its useed to hold instructions or data frequently used and its faster then RAM also expensive
  • Number of cores
    A core is a complete processing unit - with CU,ALU register etc
    Each core can independently carry out the FDE cycle
    Allows multiple instructions to be proceesed at the same time
  • Pipelining:
    Techinque of fetching an instruction while the prior one is being deocoded and the one before is being executed
  • Pipeline Controller:
    Has to predict jump instruction in order to keep the pipe full. If the controller makes a mistake the pipelines have to flushed which degrades the performance
  • Structure and function of the processor:
  • Control Unit (CU):
    • Sends out control signals to other parts of the CPU
    • Executes programs by following the fetch to code execute cycle
    • Contains the clock which coordinates CPU activity
    • Contains the decoder
    • ALU carries out calculations and logical operations upon the data
  • Registers:
    • Program Counter (PC): holds the address in memory of the next instruction
    • Memory Address Register (MAR): stores the address of data fetched from or sent to memory
    • Memory Data Register (MDR): stores the data fetched from or stored into memory
    • Current Instruction Register (CIR): stores the most recently fetched instruction waiting to be decoded and executed
    • Accumulator (ACC): holds the results of calculations and operations performed by the ALU
  • Buses:
    • Address bus: provides a memory address to system memory or input/output devices
    • Data bus: transfers data between the CPU and memory or I/O devices
    • Control bus: provides control signals for memory or I/O operations
  • Fetch to code execute cycle:
    • Program counter copies the address of the next instruction to the memory address register
    • Control unit loads the address onto the address bus
    • Control unit triggers a read signal causing main memory to place the instruction on the data bus
    • Instruction on the data bus is loaded into the memory data register
    • Memory data register copies the instruction into the current instruction register
    • Program counter is incremented by one to point to the next instruction
  • Factors affecting CPU performance:
    • Clock speed
    • Overclocking
    • Cache
    • Number of cores
    • Pipelining
  • Von Neumann, Harvard, and contemporary processor architectures:
    • Von Neumann architecture
    • Harvard architecture
    • Modern architecture with parallel processing, array processing, and multi-core processing
  • Types of processors:
    • CISC (Complex Instruction Set Computing)
    • RISC (Reduced Instruction Set Computing)
    • GPUs and their usage
  • Input, output, and storage:
  • Input devices: allow data to be entered into a computer
    • Examples: keyboard, mouse, microphone, scanner, joystick
  • Output devices: allow information to be retrieved from a computer
    • Examples: printer, speakers, monitors, actuators
  • Storage devices: used to hold data and programs for the long term
    • Categories: magnetic, flash, optical
  • RAM and ROM:
    • RAM (Random Access Memory): temporary storage for running programs and data
    • ROM (Read-Only Memory): non-volatile memory, often used for BIOS
  • Virtual storage:
    • Based on storing data over the internet
    • Advantages: accessibility, scalability, data sharing
    • Disadvantages: internet dependency, cost, security concerns
  • Cloud storage:
    • A type of virtual storage
    • Growing in popularity due to internet access and speed improvements
  • Operating system types:
    • Multitasking operating system: allows the user to do multiple things at the same time
    • Multi-user operating system: allows users to share resources of one powerful machine
    • Distributed operating system: runs across multiple individual computers but appears as one system to the end user
    • Embedded OS: found in hardware serving a single purpose
    • Real-time operating system: reacts to input as close to real time as possible
  • Device drivers contain software that tells the operating system how to understand data from external hardware devices and the format it expects to receive the data in