1.1.1 Structure and function of the processor

• Control Unit (CU):

  • Sends out control signals to other parts of the CPU
  • Executes programs by following the fetch decode execute cycle
  • Contains the clock which coordinates CPU activity
  • Contains the decoder
  • Arithmetic Logic Unit (ALU) carries out calculations and logical operations
• Registers:

  • Program Counter (PC): holds the address in memory of the next instruction
  • Memory Address Register (MAR): stores the address of data fetched from or sent to memory
  • Memory Data Register (MDR): stores the data fetched from or stored into memory
  • Current Instruction Register (CIR): stores the most recently fetched instruction waiting to be decoded and executed
  • Accumulator (ACC): holds the results of calculations and operations performed by the ALU
• Buses:

  • Address bus: provides memory address to system memory or input/output devices
  • Data bus: transfers data between CPU and memory or I/O devices
  • Control bus: provides control signals for memory or I/O operations
• Fetch to code execute cycle:

  • Fetch: program counter copies address of next instruction to memory address register, The Control Unit loads address onto address bus, The Control Unit triggers read signal to Control Bus that causes Main Memory (RAM) to place the data on the Data Bus , loads instruction to memory data register, copies instruction to current instruction register, increments program counter
  • Decode: contents of current instruction register sent to control unit, decoded by control unit
  • Execute: instruction within current instruction register carried out by CPU
• Factors affecting CPU performance:

  • Clock speed: higher speed allows more instructions per second
  • Overclocking: altering clock speed for faster performance
  • Cache: fast memory in CPU for frequently used data
  • Number of cores: each core can independently carry out fetch to code execute cycle
  • Pipelining: fetching an instruction while prior one is being decoded and executed
• Von Neumann, Harvard, and contemporary processor architectures:

  • Von Neumann: single control unit and ALU, works sequentially through instructions, stores instructions and data together in same memory unit
  • Harvard: splits memory into data and program parts, accessed with different buses
  • Contemporary: uses parallel processing, includes pipelining, array processing(e.g SIMD), and multi-core processing(MIMD)
• Fetch-Decode-Execute-Execute:

  After the memory is written to LDA or STA then address stored within the CIR will be loaded in the MAR. The STA data is stored in the ACC is sent to memory.If the Data is written as LDA the data is loaded from the memory into the ACC