1.1.1

Cards (12)

    • Data Bus: transports data and instructions between components
    • Address Bus: transmits memory addresses
    • Control Bus: transmits control signals between internal and external components
  • Components of a Processor:
    • The Arithmetic and Logic Unit (ALU) completes all arithmetical and logical operations
    • The Control Unit directs the operations of the CPU
    • Registers:
    • Program Counter (PC) holds the address of the next instruction to be executed
    • Accumulator (ACC) stores the results from calculations
    • Memory Address Register (MAR) holds the address of a location to be read from or written to
    • Memory Data Register (MDR) temporarily stores data
    • Current Instruction Register (CIR) holds the current instruction being executed, divided into operand and opcode
    • Buses:
  • Assembly language:
    • Uses mnemonics to represent instructions
    • Instruction divided into operand and opcode in the Current Instruction Register
    • Operand contains data or address of data for the operation
    • Opcode specifies the type of instruction
  • Fetch-Decode-Execute Cycle:
    • Sequence of operations to execute an instruction
    • Fetch phase: address from PC copied to MAR, instruction copied to MDR, PC contents increased by 1, MDR value copied to CIR
    • Decode phase: CIR contents split into operand and opcode
    • Execute phase: decoded instruction is executed
  • Factors affecting CPU performance:
    • Clock Speed: determined by the system clock, time taken for one clock cycle to complete
    • Number of Cores: independent processors able to run their own fetch-execute cycle
    • Cache: CPU's onboard memory, instructions copied from main memory for quicker access
    • Level 1 Cache: very fast memory cells with small capacity
    • Level 2 Cache: relatively fast memory cells with medium capacity
    • Level 3 Cache: larger and slower memory cells
  • Pipelining:
    • Process of completing fetch, decode, and execute cycles of three separate instructions simultaneously
    • Instruction pipelining separates fetching, decoding, and executing
    • Arithmetic pipelining overlaps arithmetic operations
  • Computer Architecture:
    • Von Neumann Architecture: shared memory and data bus for both data and instructions
    • Harvard Architecture: physically separate memories for instructions and data, used with embedded processors
    • Contemporary Processor Architecture: combination of Harvard and Von Neumann, dividing cache into instruction and data cache
  • buses are a set of parallel wires which connect two or more components inside the CPU.
  • the width of the bus is the number of parallel wires the bus has. the width of the bus is directly proportional to the number of bits that can be transferred simultaneously at any time
  • control signals for the control bus include:
    • bus request
    • bus grant
    • memory write
    • memory read
    • interrupt request
    • clock
  • advantages of von neumann architecture:
    • cheaper to develop as the control unit is easier to design
    • programs can be optimised in size
  • advantages of harvard architecture:
    • quicker execution as data and instructions can be fetched in parallel
    • memories can be different sizes which can make more efficient use of space