Von Neumann Architecture: shared memory and data bus for both data and instructions
Harvard Architecture: physically separate memories for instructions and data, used with embedded processors
Contemporary Processor Architecture: combination of Harvard and Von Neumann, dividing cache into instruction and data cache
buses are a set of parallel wires which connect two or more components inside the CPU.
the width of the bus is the number of parallel wires the bus has. the width of the bus is directlyproportional to the number of bits that can be transferred simultaneously at any time
control signals for the control bus include:
bus request
bus grant
memory write
memory read
interrupt request
clock
advantages of von neumann architecture:
cheaper to develop as the control unit is easier to design
programs can be optimised in size
advantages of harvard architecture:
quicker execution as data and instructions can be fetched in parallel
memories can be different sizes which can make more efficient use of space