A-level OCR CS 1.1.1

• The processor is the brain of a computer
• It executes instructions which allows programs to run
• Arithmetic and Logic Unit (ALU)
• Completes all arithmetical and logical operations
• Arithmetical operations include addition and subtraction on fixed or floating point numbers
• Logical operations include boolean logic operations such as AND, OR, NOT, and XOR
• Control Unit
• Directs the operations of the CPU
• Jobs include:

  • Controlling and coordinating the activities of the CPU
  • Managing the flow of data between the CPU and other devices
  • Accepting the next instruction
  • Decoding instructions
  • Storing the resulting data back in memory
• Registers
• Small memory cells that operate at a very high speed
• Used to temporarily store data
• All arithmetic, logical and shift operations occur in these registers
• Types of registers:

  • Program Counter (PC): Holds the address of the next instruction to be executed
  • Accumulator (ACC): Stores the results from calculations
  • Memory Address Register (MAR): Holds the address of a location to be read from or written to
  • Memory Data Register (MDR): Temporarily stores data
  • Current Instruction Register (CIR): Holds the current instruction being executed, divided into operand and opcode
• Buses
• A set of parallel wires which connect two or more components inside the CPU
• Three buses in the CPU: data bus, control bus, and address bus
• Collectively called the system bus
• Data Bus:

  • Bi-directional bus used for transporting data and instructions between components
  • Address Bus:
  • Used to transmit memory addresses specifying where data is to be sent to or retrieved from
  • Control Bus:
  • Bi-directional bus used to transmit control signals between internal and external components
  • Control signals include bus request, bus grant, memory write, memory read, interrupt request, and clock
• Assembly language
• Uses mnemonics to represent instructions
• Example: ADD represents addition
• Instruction divided into operand and opcode in the Current Instruction Register
• Operand contains the data or address of the data upon which the operation is to be performed
• Opcode specifies the type of instruction to be executed
• Pipelining
• Process of completing fetch, decode, and execute cycles of three separate instructions simultaneously
• Aimed to reduce the amount of the CPU which is kept idle
• Separated into instruction pipelining and arithmetic pipelining
• Instruction pipelining separates out fetching, decoding, and executing
• Arithmetic pipelining breaks down arithmetic operations and overlaps them as they are performed
• Fetch-Decode-Execute Cycle
• Sequence of operations to execute an instruction:

  • Fetch phase: Address from PC copied to MAR, instruction copied to MDR, PC contents increased by 1, MDR value copied to CIR
  • Decode phase: CIR contents split into operand and opcode
  • Execute phase: Decoded instruction is executed
• Factors affecting CPU performance
• Clock speed, number of cores, and amount/type of cache memory
• Clock speed:

  • Determined by the system clock
  • Time taken for one clock cycle to complete
  • All processor activities begin on a clock pulse
  • Each CPU operation starts as the clock changes from 0 to 1
• Number of cores:

  • An independent processor able to run its own fetch-execute cycle
  • Multiple cores can complete more than one fetch-execute cycle simultaneously
• Cache memory:

  • CPU's onboard memory
  • Instructions fetched from main memory are copied to cache for quicker access
  • Cache types: Level 1, Level 2, Level 3
• Computer Architecture
• Von Neumann Architecture:

  • Basic components include single control unit, ALU, registers, and memory units
  • Shared memory and shared data bus used for both data and instructions
  • Built on the stored program concept