15 Hardware and Virtual Machines

• Why is Boolean Algebra used?

  - To simplify complex logic circuits to provide an equivalent output

  - Using less components to make them more reliable, generate less heat, faster, and cheaper
• JK Flip Flops

  - Prevents racing states

  - By using extra gates + clock input to synchronise 2 inputs
• SR Flip Flop Using NAND Gates

  Active Low System (default state = 1)
• SR Flip Flop using NOR gates


  Active High System (default value = 0)
• Flip Flop

  - Acts like a single bit of memory

  - Maintains a stable output that can only be changed by an input pulse/power loss

  - Changes to inputs made as a pulse, before resetting to default state

  - Produces an output + complement of output
• Full Adder Circuit

  - 2 half adders combined to allow sum of several bits

  - 3 inputs; 1st bit, 2nd bit, and carry value
• Benefits of using NAND or NOR gates

  - Universal; any logic circuit can be made using them

  - Easy to manufacture, making them cost efficient
• Half Adder Circuit

  - Carries out binary addition, taking 2 inputs and producing two output bits (sum and carry)
• Drawbacks of Virtual Machines

  - Performance much slower than Host OS

  - Can be complex + expensive to create

  - Not possible to emulate some hardware
• Benefits of Virtual Machines

  - Self contained: Guest OS has no impact on hardware/software outside VM, errors will not cause system crashes

  - Can run apps which are not compatible with host OS

  - Useful for old/discontinued software

  - Useful for testing new software

  - Multiple VMs can be run simultaneously
• Running an App using Guest Operating Systems

  - GOS do not know they are running as VMs

  - GOS behave as if they are a regular OS, believing they are interacting with host hardware

  - When in reality, the VM software takes their requests and passes them to the host OS
• Features of VM on a Host Operating System


  - OS that controls physical hardware

  - Usual OS for the host computer

  - OS runs the virtual machine software
• Features of VM on a Guest Operating System

  - The OS running in a VM controls the virtual hardware during emulation

  - OS being emulated within the host OS

  - OS running under control of the host OS
• Virtual Machine

  Program that behaves like an actual computer/OS

  - Use of software to implement a hardware set up

  - Sandboxed
• Parallel

  Executes multiple instructions simultaneously
• Massive

  Thousands of microprocessors
• Where MIMD is used

  In multi core systems like supercomputers
• MIMD

  - Multiple processors receiving parallel data streams

  - Each processor unit, with dedicated cache memory, executes a different instruction concurrently
• Where MISD is used

  Fault tolerance systems

  - Same data fed into multiple processors, output only accepted if all outputs are identical
• MISD

  Multiple processors carry out multiple instructions on the same data stream
• Where SIMD is used

  Graphic Cards

  - Each pixel allocated to a processor

  - Adjustments happen simultaneously to maintain a consistent image
• SIMD

  Single instruction applied to multiple elements of data at one time across multiple processors AKA array processors
• Where SISD is used

  Found in earlier personal computers with simple applications
• SISD

  - Sequential architecture; one data stream + one instruction stream at a time

  - One single process is carried out at one time on a single core processor
• Drawbacks of Parallel Processing

  - Unsuitable for processing dependent data

  - Much more expensive hardware required
• Benefits of Parallel Processing

  - Faster method of processing for dependent data

  - Removes 'bottlenecking' issue within VN architecture = lower latency
• Describe parallel processing

  - Where a process is split up; different parts are carried out by different processors simultaneously

  - Communication is important, as data may need to be passed between processors
• How to resolve WAR

  - Scheduling

  - All instructions use 5 stages; read instructions resolve in stage 2, write in stage 5
• Write After Read

  - Earlier instruction reads a value from the same place that will be written to by a later instruction

  - Later instruction writes its result before first instruction has read it
• How to resolve WAW

  Renaming - modify second write to put its result in a different register
• Write After Write


  - Earlier instruction writes a result to the same place a later instruction writes to

  - 2nd instruction may write its result before 1st instruction
• How to resolve RAW

  Stalling - identify error and wait until write is resolved
• Read After Write


  - One instruction calculates a value that is used by a later instruction

  - Value may not be ready when second instruction reads it
• What happens to the multiple instructions in the pipeline if an interrupt occurs?

  1. Pipeline contents can erase latest four instructions + normal interrupt handling routine can be applied to the remaining instruction

  2. Construct individual PC registers within processor to store current data so that it can be restored once interrupt is serviced
• Use of pipelining + registers in RISC processors

  - Allows multiple instructions to be processed simultaneously, without waiting until previous instruction is complete to begin the next

  - Allows for more efficient use of resources

  - Speeds up FE cycle
• RISC v CISC

  - RISC uses simple instructions from a smaller instruction set, whilst CISC uses complex instructions from a larger instruction set to reduce the # of instructions used

  - RISC has fewer instruction sets + addressing modes than CISC

  - RISC uses single clock cycle instructions, CISC uses multi-clock cycle instructions

  - RISC uses instructions of a fixed length, CISC can use instructions of variable lengths

  - RISC executes instructions in a shorter time than CISC

  - RISC extensively uses general multi purpose registers

  - It is more complex to decode instructions using CISC

  - It is easier to make pipelining work using RISC

  - RISC has a design emphasis on software, CISC has design emphasis on hardware

  - RISC heavily uses RAM, CISC uses RAM more efficiently

  - RISC splits cache between data and instructions, CISC extensively uses cache
• Components of Instruction Set Architecture

  1. Instruction Set

  2. Instruction Format

  3. Addressing modes

  4. Registers accessible by instructions
• Microprogrammable

  1. Control signals are made by software microinstructions; easy to modify

  2. Cheaper; software costs < hardware costs

  3. Can handle complex instructions

  4. Code is translated into microinstructions to generate control signals, CU operates slower

  5. Microinstructions can be modified/updated for greater flexibility

  6. Stored in memory
• Hardwired

  1. Control signals generated by hardware logical circuits, hard to modify

  2. Dedicated circuit for each possible instruction

  3. More expensive - hardware costs

  4. Cannot handle complex instructions; each instruction must be hardwired

  5. Hardware generates control signals, CU operates faster
• MicroProgrammable is used in

  CISC