Arithmetic Logic Unit (ALU) completes arithmetic and logical operations
Control Unit (CU) directs operations of CPU, controls/coordinates CPU activities, manages flow of data between CPU and other devices, accepts next instruction, and stores resulting data in memory
Dedicated/special purpose Registers:
Programme Counter (PC) holds address of next instruction to be executed
Accumulator (ACC) stores results of calculations performed by ALU
Memory Address Register (MAR) holds address of a location to be read from/written to
Memory Data Register (MDR) temporary data store for data to be read/written
Current Instruction Register (CIR) holds current instruction the processor is executing and splits code into opcode and operand
General purpose registers: ALU connected to general purpose registers used to keep results of intermediate calculations produced as part of a larger computation
Clock: systems clock generates regular clock pulses to synchronize operations of processor components, with rising and falling edges, clock period, and clock rate calculated as the number of clock cycles completed in one second
Fetch:
PC keeps address of next instruction to be executed
Contents of PC copied to MAR connected to address bus
Address of next instruction placed on address bus
Control unit instructs memory read operation to transfer contents of memory location to processorInstruction stored at that address transferred to processor and saved in MDR
PC incremented by 1
Contents of MDR copied to CIR
Fetch-Decode-Execute cycle:
Applies to both application and system software
Before the cycle can take place, program instructions must be translated into machine code and loaded into main memory
At the end of each cycle, the processor checks the status register for errors/interrupts/exceptions
The processor:
CPU processes data by executing low level instructions in machine code
Instructions need to be transferred from secondary storage into main memory to be fetched, decoded, and executed
Data to be accessed is loaded into main memory or provided by input/output devices via I/O controllers
Buses:
Components of a computer system are connected using buses for data transfer
Systems bus is set of parallel connections allowing internal components to communicate and exchange data, made up of address, data, and control bus in Von Neumann architecture
Data bus transfers data/instructions bidirectionally
Address bus specifies memory location address unidirectionally
Control bus sends control signals to manage operations and exchange status signals between components, bidirectional
Factors affecting processor performance:
clock speed
number of cores
cache size
Multiple cores allow instructions to be completed in parallel, but doubling cores doesn't directly double performance
Cache is a fast, small capacity storage for frequently used data/instructions, but there is a trade-off with size affecting search time
Clock speed affects how fast instructions are carried out
Instructional Pipelining allows multiple instructions to be processed simultaneously for efficiency
Von Neumann architecture consists of processor, memory unit, connections for inputs/outputs, and secondary storage, using address and data buses for both instructions and data
Harvard architecture keeps instructions and data in separate memory locations, using separate data and address buses, commonly used in embedded systems
Decode:
CU decodes instruction in CIR
Instruction split into operand and opcode
Execute:
Instruction is executed
Sequence of operations depends on type of instruction