Matt's Exam

• MSP-EXP432E401Y VIH = 2.145V
• MSP-EXP432E401Y VIH = 1.155V
• • Data is stored in “little endian” format: the lowest address byte contains the least significant byte of the data
• The most important ranges for us are: • Flash: 0x0000.0000 to 0x000F.FFFF • SRAM: 0x2000.0000 to 0x0003.FFFF • Registers controlling peripherals and I/O: starting at 0x4000.0000
• The least significant hex digits must be 0, 4, 8, or C
• Each group has a base address pointing to the starting address for that particular group • Each register within the group has an offset from the base 


  register addr base = addr + offset
• resolution = Vfs / 2^n
• quantization error -

  v - N/2^n *Vfs
• The SAR algorithm has a fixed conversion time, independent of the input value: , where n is the number of bits and TC is the clock period
• An under-sampled (aliased) signal will still look like a valid signal. This is why it is so important to guard against aliasing
• f sample >= 2f signal
• fvco = M*fref

  
• The MSP-EXP432E401Y has two clock sources: a 25 MHz Main Oscillator (MOSC) and a 16 MHz Precision Internal Oscillator (PIOSC)
• The PLL can be activated or deactivated
• On POR, the clock source is the PIOSC and the PLL is deactivated → system clock is 16MHz
• The MSP-EXP432E401Y can be configured to run up to 120 MHz.
• Don’t use any frequency less than 5MHz.
• System clock (SYSCLK) typically derived from Precision Internal Oscillator (PIOSC) or Main Oscillator (MOSC/mosc)
• The microcontroller powers up with PIOSC running at 16 MHz
• The MSP-EXP432E401Y derives the Main Oscillator from a 25MHz crystal oscillator.
• If the clock is changed, then ALL connected subsystem clocks speeds + SYSCLK are changed
• PLL can be controlled by MOSC or PIOSC and PLL can be bypassed
• • SysTick is a counter that counts down at the system frequency.
• SysTick is a 24-bit down counter that counts down at the bus clock frequency.
• SysTick can be operated in polling or interrupt mode.
• Delay = (RELOAD + 1) / fSYSCLK
• duty cycle formula - D = H/(H+L) *100
• The percent time set high is called the duty cycle .
• Data Flow Graphs - Top level organization, but not refined enough for coding or debugging.
• flowcharts - Present a logical flow using defined symbols. • When suitably refined, a program can be easily written directly from the flow chart. • Very helpful for communicating your design and debugging.
• Since we have a loop, this simple program implements polling. • Polling means looping based upon a value we keep checking (e.g., was a button pressed?). • A polling method does not exclude the use of interrupts.
• An interrupt driven program typically has a very different structure. • Often the main body of the program seems to be missing. However, by looking at the environment set up we can determine that interrupts have been enabled. All logic has been implemented as event driven and so it is common to have an infinite loop when the processor is waiting for an event.
• Top down System organization: computation and IO requirements
• Bottom up system organization: computation and IO available
• a call graph: assists in organizing the software and defining the types of data. To reduce complexity try to minimize the number of arrows
• Data flow graph: A representation on how data flows through a system
• stack in embedded system: The micro saves state info and return address using stack
• Queue in embedded system: when sampling data via adc or when reading data from a peripheral. Sometimes data cant be processed between samples so u queue them
• Priority Queue: Uses interrpts the requests are queued for handling by service routines. Priority helps them jump the line
• EPROM: erasable programmable read only memory. Non volatile. must be bulk erased