1.1.1 Structure and Function of the Processor

• The ALU (Arithmetic and Logic Unit) completes all of the arithmetical and logical operations.
• Logical operations include boolean logic operations such as AND, OR, NOT, and XOR
• The Control Unit is the component of the processor which directs the operations of the CPU
• The control unit has the follows jobs of:

  1. Controlling and coordinating the activities of the CPU
  2. Managing the flow of data between the CPU and other devices
  3. Accepting the next instructions
  4. Decoding Instructions
  5. Storing the resulting data back in memory
• Registers are small memory cells that operate at a very high speed. They are used to temporarily store: arithmetic, logical and shift operations.
• The registers are the: Program counter (PC), Accumulator (ACC), Memory Address Register (MAR), Memory Data Register (MDR), Current instruction register (CIR)
• The Program Counter (PC): Holds the address of the next instruction to be executed.
• Accumulator (ACC): Stores the results from calculations
• Memory Address Register (MAR): Holds the address of a location that is to be read from or written to.
• Memory Data Register (MDR): Temporarily stores data that has been read or data that needs to be written.
• Current Instruction Register (CIR): Holds the current instruction being executed, divided up into operand and opcode.
• Buses are a set of parallel wires which connect two or more components in the cpu. There are 3 busses the: control bus, address bus and data bus. These busses collectively is called the system bus.
• Data Busses are a bi-directional bus (meaning bits can be carried in both directions). This is used for transporting data and instructions between components.
• Address bus is used to transmit the memory addresses, specifying where data is to be sent to or retrieved from. The width of the address bus is proportional to the number of addressable memory locations.
• Control Bus is a bi-directional bus used to transmit control signals between internal and external components.
• The control signals include:

  • Bus request: shows that a device is requesting the use of the data bus
  • Bus grant: shows that the CPU has granted access to the data bus
  • Memory write: data is written into the addressed location using this bus
  • Memory read: data is read from a specific location to be placed onto the data bus,
  • Interrupt request: shows that a device is requesting access to the CPU
  • Clock: used to synchronise operations
• Assembly language divides machine code into OPERAND and OPCODE into the current instruction register. The operand contains the data or the address of the data inputted. The opcode specifies the type of instruction to be executed.
• Pipelining is where the fetch, decode and execute cycle is done simultaneously. For example is can fetch and execute at the same time.
• Pipelining reduces the amount of time CPU which is kept idle. It is separated into instruction pipelining and arithmetic pipelining. Instruction pipelining is separating out the instruction into fetching, decoding, and executing. Arithmetic pipelining is breaking down the arithmetic operations and overlapping them.
• Fetch phase:

  • Address from the PC is copied to the MAR
  • Instruction held at that address is copied to MDR by the data bus
  • Simultaneously, the contents of the PC are increased by 1
  • The value held in the MDR is copied to the CIR
• Decode phase:

  • The contents of CIR are split into operand and opcode
• Execute phase:

  • The decoded instruction is executed
• Three factors that affect CPU performance: clock speed, number of cores and the amount and type of cache memory.
• Clock speed:

  Clock speed is determined by a system clock. All processor activities begin on a clock pulse, and each CPU operation starts as the clock changes from 0 to 1. The clock speed is the time taken for one clock cycle to complete.
• Number of cores:

  A core is an single processor that runs its own fetch-execute cycle. A computer with multiple cores can complete more than one fetch-execute cycle at any given time. However, not all programs are able to utilise multiple cores efficiently as they have not been designed to do so, so this isn't always possible.
• Cache memory is the CPU’s onboard memory. Instructions fetched from main memory are copied to the cache, so if required again, they can be accessed quicker. As cache fills up, unused instructions are replaced.
• Level 1 Cache has Very fast memory cells with a small capacity. (2-64KB)
• Level 2 Cache has Relatively fast memory cell, with a medium sized capacity. (256KB-2MB)
• Level 3 Cache has a much larger and slower memory cell .
• Von Neuman Architecture includes basic components of a computer: ALU, memory, buses, registers, and is built on the stored data program
• Harvard architecture separates instruction and data storage into two separate memories, which allows them to be read simultaneously by different parts of the system.
• advantages of the vna is that it is cheaper to develop as the control unit is easier to design.
• advantages of the vna is that programs can be optimised in size.
• Advantages of the HA is that it has Quicker execution as data and instructions can be fetched in parallel.
• Advantages of the HA is that data is in different sizes, which can make more efficient use of space.