Components of a computer

• Central Processing Unit (CPU)


  Also known as the processor, has a number of different components which enable it to carry out its task of executing instructions
• Components of the CPU

  • Control unit
  • Buses
  • Arithmetic Logic Unit (ALU)
  • Dedicated registers
• Control Unit


  Controls and coordinates the activities of the CPU, directing the flow of data between the CPU and other devices. It accepts the next instruction, decodes it into several sequential steps such as fetching addresses and data from memory, manages its execution and stores the resulting data back in memory or registers
• Bus


  A set of parallel wires connecting two or more components of a computer. It typically consists of 8, 16, 32 or 64 lines
• Accessing main memory


  1. Processor sends address on address bus

  2. Data in that location is returned to CPU on data bus

  3. Control signals are sent along the control bus
• System bus


  The collective term for the data, address and control buses that connect the processor, memory and I/O controllers
• Data and control signals travel in both directions between the processor, memory and I/O controllers
• Addresses travel only one way along the address bus: the processor sends the address of an instruction, or of data to be stored or retrieved, to memory or to an I/O controller
• Control bus


  A bi-directional bus, meaning that signals can be carried in both directions
• Direction of transmission along the buses


  1. The data and address buses are shared by all components of the system

  2. Control lines must be provided to ensure that access to and use of the data and address buses by the different components of the system does not lead to conflict
• Purpose of the control bus

  To transmit command, timing and specific status information between system components
• Control lines


  • Bus Request: indicates that a device is requesting the use of the data bus
  • Bus Grant: indicates that the CPU has granted access to the data bus
  • Memory Write: causes data on the data bus to be written into the addressed location
  • Memory Read: causes data from the addressed location to be placed on the data bus
  • Interrupt request: indicates that a device is requesting access to the CPU
  • Clock: used to synchronise operations
• Data bus


  A bi-directional path for moving data and instructions between system components, typically consisting of 8, 16, 32 or 64 separate lines
• Word


  A fixed size group of digits, typically 16, 32 or 64 bits, which is handled as a unit by the processor
• Address bus


  Transmits the memory addresses of words that are used as operands in program instructions, so that the data can be retrieved and sent back to the processor
• Storing results


  When an instruction has been performed and the result is to be stored at a particular memory location, it is transmitted via the data bus
• Arithmetic-Logic Unit (ALU)


  Performs arithmetic and logical operations on data, such as SUBTRACT, MULTIPLY, DIVIDE on fixed or floating point numbers. Can also perform bit shifting operations and Boolean logic operations like AND, OR, NOT, XOR.
• Registers


  • Special memory cells that operate at very high speed. Results of arithmetic, logic or shift operations are temporarily stored in registers. Typically up to 16 general purpose registers in the CPU.
• Accumulator


  A single register that takes the place of general purpose registers, where the results of all operations carried out in the ALU are stored.
• Special-purpose registers


  • Program Counter (PC) - holds the address of the next instruction to be executed

  Current Instruction Register (CIR) - holds the current instruction being executed, divided into operand and opcode

  Memory Address Register (MAR) - holds the address of the memory location from which data (or an instruction) is to be fetched or to which data is to be written

  Memory Data Register (MDR) - used to temporarily store the data read from or written to memory
• The Fetch-Decode-Execute cycle


  1. Fetch

  2. Decode

  3. Execute
• The sequence of operations involved in executing an instruction can be divided into three phases - fetching, decoding and executing it. This cycle is repeated over and over as each instruction of the program is executed
• Fetch phase


  • The address of the next instruction is copied from the program counter (PC) to the memory address register (MAR)
  • The instruction held at that address is copied to the memory data register (MDR)
  • The content of the PC is incremented so that it holds the address of the next instruction
  • The contents of the MDR are copied to the current instruction register (CIR)
• Decode phase


  • The instruction held in the CIR is decoded
  • The instruction is split into opcode and operand
  • The opcode is used to determine the type of instruction and what hardware to use to execute it
  • The operand holds either the address of the data to be used with the operation, which is then copied to the MAR, or the actual data to be operated on, which will be copied to the MDR
• Execute phase


  • The appropriate instruction/opcode is carried out on the operand
• Clock speed


  The system clock generates a series of signals, switching between 0 and 1 several million times per second and synchronising CPU operations. Each CPU operation starts as the clock changes from 0 to 1 (or in some systems from 1 to 0), and the CPU cannot perform operations faster than the clock cycle (the time the clock takes to go from 0 to 1 and back to 0)
• Clock speed


  Measured in Gigahertz (GHz), about 1 billion cycles per second. Typical speeds for a PC are between 2 and 4 GHz. The greater the clock speed, the faster instructions will be executed
• Traditional (von Neumann) computer


  • Instructions are fetched and executed one at a time in a serial manner
• Multi-core processor


  • Has multiple processors linked together in the same integrated circuit. A dual-core processor has two processors, a quad-core has four
• Multi-core processor


  Each core is theoretically able to process a different instruction at the same time with its own fetch-execute cycle, making the processor two or even four times faster with a quad-core chip
• Although a dual-core processor has twice the power, it does not always perform twice as fast, because the software may not always be able to take full advantage of both processors
• Cache memory


  A small amount of expensive, very fast memory inside the CPU. When an instruction is fetched from main memory it is copied into the cache so if it is needed again soon after, it can be fetched from cache, which is much quicker than going back to main memory
• Cache replacement


  As cache fills up, unused instructions or data still being held are replaced with more recent ones
• Components of a computer

  • CPU
  • Cache
  • Main memory
• CPU


  • There are different "levels" of cache
• Level 1 cache


  Extremely fast but small (between 2-64KB)
• Level 2 cache


  Fairly fast and medium-sized (256KB-2MB)
• Some CPUs also have Level 3 cache
• Data bus


  Transmits the data held in a word of memory, between processor components and memory
• Operand


  The largest value that can be held in a word, related to the size of the data bus