Stages of the Interrupt Service Routine
1. Interrupt register checked at the end of each Fetch-Decode-Execute cycle
2. If there is an interrupt exists with a higher priority to the current process, the current contents of the registers in the CPU are transferred into a stack
3. The relevant interrupt service routine (ISR) is loaded into RAM
4. A flag is set to signal the ISR has begun
5. The flag is reset once the ISR has finished
6. Interrupt register checked again. If interrupts are of a higher priority, the process is repeated
7. If there are no interrupts with a higher priority, the contents of the stack are popped and place back into the special memory registers
8. The fetch-Decode-Execute cycle renews as before