1.1 structure & function of the processor

• The ALU performs all the arithmetic and logical operations of the CPU, including:

  • addition and subtraction, multiplication and division
  • comparisons such as whether numbers are equal or if one is greater than another
  • boolean operations such as AND, OR and NOT
• The control unit (CU):

  • sends out control signals to other parts of the CPU
  • executes program instructions by following the fetch-decode-execute cycle
  • made up of two key parts:

  1. the clock - coordinates the CPU's activity
  2. the decoder - decodes program instructions
• Registers:

  • tiny amounts of super-quick memory within the CPU
  • used to hold information needed for CPU to work
  • each register holds a specific piece of information
• Memory Address Register (MAR):

  • holds the address of the location in memory where data is to be retrieved or stored
• Program Counter (PC):

  • holds memory location address of next instruction to be performed by the CPU
  • PC doesn't store the instruction itself
• Accumulator:

  • holds result of calculations and operations performed by the ALU
• Memory Data Register:

  • holds data that has been retrieved from memory, or that is about to be stored in memory
• Current Instruction Register (CIR):

  • used to store the current instruction that the CPU is working on
• Buses:

  • used to send and receive data and instructions from main memory (RAM)
• Von Neumann CPU has 3 buses which are the data bus, the address bus and the control bus
• Data bus:

  • retrieves data and instructions from main memory
• Address bus:

  • sends addresses to main memory
• Control bus:

  • sends signals to other devices inside the computer system
• Fetch ->

  • address of next instruction to be processed is copied from the PC to the MAR
  • PC is incremented to point to next instruction that will be needed when cycle starts again
  • Instruction stores at location held by MAR is copied to the MDR
• Decode ->

  • CU decodes the instruction and sends control signals to component within or outside CPU that needs to act
• Execute ->

  • operation indicated by instruction is performed by appropriate component
  • e.g. ALU performs operation given by CU
  • e.g.2 value stores by the PC or MAR might be changed
• Cache memory ->

  • small amount of very fast memory inside CPU
  • in comparison to cache, accessing RAM is a very slow operation
  • by storing frequently accessed data and instructions in cache memory, we can avoid the process of accessing the RAM
• Clock speed ->

  • CPU's clock sends a pulse at fixed intervals to trigger next stage of fetch, decode, execute (FDE) cycle
  • higher the clock speed, the more pulses are sent per second, so more instructions can be executed in the same amount of time
• Cores ->

  • each core of a CPU is capable of processing instructions independently
  • each core has its own CU and ALU, but the cores share access to cache and main memory
  • multiple cores allows a CPU to process multiple instructions at the same time
• Pipelining is a feature which allows more processor operations to take place in less time.
• Processors typically complete one instruction before moving on to the next. This means parts of the processor are idle while the instruction is completed. This is an inefficient process.
• Effects of pipelining ->

  • Pipelines ensure as much of the processor is in use all at one time and increase efficiency of the computer system.
  • Pipelining is usually split into two pipelines:
  • Instruction Pipeline.
  • Arithmetic Pipeline.
• Instruction pipeline (pipelining) ->

  • The instruction pipeline will pre-fetch the next instruction and data and store it in a register.
  • As one instruction leaves the current instruction register (CIR), the next one is ready to be loaded and decoded.
  • At any given point, there are instructions being fetched, decoded and executed.
• Arithmetic pipeline (pipelining) ->

  • The arithmetic pipeline divides up an arithmetic operation into its individual steps.
  • Each step is performed overlapping the next step.
• Pipelining ensures a continuous flow of instructions in the fetch, decode, execute cycle. This makes a processor run more efficiently.
• Von Neumann Architecture ->

  • The main architecture that we use today is the Von Neumann architecture.
  • It was designed in the 1940s by John von Neumann.
• Von Neumann Architecture (programs) ->

  • The architecture works on the stored program concept:
  • A program must be stored in main memory to be executed.
  • Its instructions are fetched one at a time and executed serially.
• VN Architecture (units, registers & buses) ->

  • The Von Neumann architecture uses:
  • One control unit.
  • One arithmetic logic unit.
  • Five registers.
  • Three buses.
• Harvard Architecture ->

  • Harvard architecture has two memory locations, one for data and one for instructions.
  • The instructions are often unchanging so will be kept in Read Only Memory (ROM).
• Uses of Harvard Architecture ->

  • Harvard architecture processors are mainly used in digital signal processing applications such as:
  • Medical body signal monitoring.
  • Sonar.
• Contemporary Architecture ->

  • Although modern PC processors are still based off the Von Neumann architecture, they often have elements of Harvard architecture and other elements for efficiency.
• Differences to Von Neumann ->

  • The cache inside a modern processor is split into two storage locations for data and instructions and these are accessed using a Harvard style system.
  • Processors now also have multiple cores and pipelining which further improve efficiency and capabilities of modern processors.