Module 5 ECE part 1

• FET is generally a three terminal device which could be used in applications wherein bipolar junction transistors are used.
• It is a voltage controlled device as compared to a BJT which is a current

  controlled device.
• The term field effect is used because for FETs, an electric field established by the carriers controls the conduction path of the output current without the need for direct contact between the input signal parameters and the output signal parameters.
• It is a unipolar device because current flow is only dependent on either electron flow (n channel) or hole flow (p channel)
• BJT is a bipolar device because current flow is always dependent on electron flow (n material) and hole flow (p material).
• FETs have very high input impedance (1 Mohm to hundreds of Mohm or higher), because the p n junction at the input is operated in the reverse biased condition (for JFET), the gate is insulated (for MOSFET), or the gate has a Schottky barrier (for MESFET). This is higher than those of BJTs
• FETs are more temperature stable compared to BJTs.
• FETs are usually smaller than BJTs making them useful in integrated circuits.
• FETs are less sensitive to changes in the applied signal compared to BJTs, resulting to smaller voltage gains than BJT voltage gain.
• FETs are usually more sensitive to handling compared to BJT.
• 3 Types of FETs

  1. JFET
  2. MOSFET/IGFET
  3. MESFET
• The n channel FET is more dominant than the p channel FET.
• Two Types of JFET:Junction field effect transistor

  1. N Channel
  2. P Channel
• Enhancement MOSFET: Metal oxide semiconductor field effect transistor

  1. Depletion MOSFET
  2. Enhancement MOSFET
• Two Types of MESFET: Metal semiconductor field effect transistor

  1. Depletion MESFET
  2. Enhancement MESFET
• Commercial MESFETs are typically made up of N channel only because N channel MESFETs are faster compared to P channel MESFETs.
• FETs could also be classified as JFET and IGFET (Insulated Gate Field Effect

  Transistor)
• JFETs have three terminals: Gate, Drain and the Source
• The Gate is used to control the flow of current flowing through the drain and the source.
• The drain current is the same as the source current. Both currents flow through the channel of the FET.
• The drain and the source are connected to both ends of the n type material for n channel, and to both ends of the p type material for p channel.
• The drain current and source current are equal in value
• Drain and source current flows through the channel
• The gate is made up of two materials which are internally connected.
• The channel is sandwiched between the two gate materials.
• Two depletion regions exist between the n type materials and p type materials.
• If the depletion region increases in width , the width of the channel decreases, and less current could flow through the channel, thus the drain and source current will be lower .
• Decrease in width of the depletion region results to higher drain current.
• The width of the depletion region can be increased by increasing the reverse bias voltage between the gate and the source and between the gate and the drain.
• Thus the drain current and source current can be controlled by changing the reverse bias voltage between the gate and the source and between the gate and the drain.
• For an n channel JFET When voltage between the gate and source (VGS ) is 0 volt , and the voltage between the drain and the source (VDS ) is positive at the Drain
• Depletion region between the Gate and the Drain is wider than the depletion region between the Gate and the Source, because the p-n junction between the Drain and the Gate is more reverse biased than the p-n junction between the Gate and the Source.
• Conventional current flows from Drain to Source through the channel, and the current is only limited by the resistance of the n channel between the drain and the source.
• Drain current (I D ) is equal to the Source current (I S).
• When Drain to Source voltage (V DS ) increases, Drain current (I D ) and Source current (I S ) also increase until V DS reaches the pinch off voltage Vp), which is the pinch off voltage when V GS = 0 Volt
• When V DS increases beyond V P , Drain current (I D) does not increase andpractically remains at a constant saturation level called I DSS (Saturation Drain Current when V GS = 0).
• This indicates that the Drain to Source resistance is approaching an "infinite" value, as any increase in V DS does not result in an increase in Drain current.
• This is caused by both depletion regions becoming very wide that they “ touch ” each other , and that they almost close the n channel (small current path still exists).
• As the Drain to source voltage (V DS ) increases beyond Vp, the region of close contact between the two depletion region increases.
• I DSS is the maximum Drain current (Source current also, I D =I S ) for the JFET when V GS = 0 volt and V DS > |V P|, as long as V DS does not reach the breakdown voltage.