Structure and Function of the Processor

• • Control Unit - Directs flow of data between CPU and other devices. Accepts next instruction, decides it, handles execution, stores result in memory or registers
  • Program Counter - Holds address of next instruction to be execution
  • MAR - Holds address of next instruction to be fetched
  • MDR - Temporarily stores data which is read from or written to memory, all data must travel down data bus and pass through MDR
  • ALU - Performs arithmetic and logical operations
  • Accumulator - General purpose register, temporarily holds result of ALU
• • Address bus - Carries memory addresses that identify where data is being read from or written to
  • Data bus - Carries the binary data that make up the actual information
  • Control bus - Carries command and control signals to and from every other component of the CPU
• Decode unit - Decodes binary data into instructions like load

  Mnemonics are also decoded here
• Fetch

  • Address in PC is copied into MAR
  • Sent along address bus to memory
  • CU sends a read signal along control bus to memory
  • Contents in memory sent along data bus to MDR
  • Copied in CIR
  • PC increments
• Decode

  • Opcode - what the instruction says to do
  • Operand - Address to perform the instruction on
  • Instruction is decoded
• Execute

  • Address in operand sent to MAR
  • Sent down address bus to main memory
  • CU sends a read signal
  • Contents sent along data bus to MDR
  • Instruction can now be performed on the data
• When an if statement comes up in a program, the address in the operand of the instruction in the CIR is copied into the PC and replaces the last value, allowing it to jump around memory instead of simply incrementing
• CPU performance

  • Clock speed - Number of F-E cycles per second (3.2GHz = 3.2 billion instruction fetched per second)
  • Cache size - temporary storage of data and instructions, located near CPU for very fast access. Holds frequently or recently used instructions
  • Core number - A core is a complete copy of a CPU, quad-core is 4 CPUs. Allowing processor to have more power to run multiple programs at once
• Pipelining is where the CPU moves onto the next instruction after fetching the previous instruction instead of dealing with them one at a time

  More efficient use of registers
• A pipeline flush might occur if the next instruction in the pipeline is no longer the next instruction to be executed due to branching.

  The processor gets rid of all instructions in the pipeline
• Von Neumann:

  • Shared memory space for instructions and data
  • Data and instructions stored in the same format
  • Single processor follows linear FDE cycle
  • Registers used as fast access to data or instructions

  Harvard:

  • Instructions and data in separate memory units
  • Each has own bus
  • Reading and writing can be done while fetching instructions
  • Used by RISC processor
• RISC (Reduced Instructions Set Computed)

  • Aims to use simple instructions that will be executed in a single clock cycle
  • More lines of assembly needed
  • Therefore the compiler has to do more work
  • More RAM needed to store assembly instructions
  • Less complex hardware is needed, meaning more room for registers and cache
• CISC (Complex Instruction Set Computer)

  • Aims to complete a task in as little lines of assembly as possible
  • Processor hardware and circuitry has been to more complicated
  • Complex instructions might require more than one clock cycle to complete
• CISC is mainly found in desktop PCs and laptops

  RISC is mainly found in low power, portable devices such as phones, smart watches, tablets, printers