1.1.1 - Structure and function of processor

• Arithmetic Logic Unit (ALU)

  • completes all of the arithmetic and logical operations
• Arithmetical Operations

  • all mathematical operations
  • eg: addition and subtraction on fixed or floating point numbers
• Logical Operators

  • boolean logic operations
  • AND, OR, NOT and XOR
• The Control Unit

  • the component of the processor that directs the operations of the CPU
• Control Unit - Jobs

  • controlling and coordinating activities of CPU
  • managing flow of data between CPU and other devices
  • decoding instructions
  • storing resulting data in memory
• Registers

  • small memory cells that operate at a very high speed
  • used to temporarily store data
  • all arithmetic, logical and shift operations occur here
• Program Counter (PC)

  • holds address of next instruction to be executed
• Accumulator (ACC)

  • stores results from calculations
• Memory Address Register (MAR)

  • holds address of location to be read from or written to
• Memory Data Register (MDR)

  • stores data that's been read or needs to be written
• Current Instruction Register (CIR)

  • holds the current instruction being executed
  • divided into operand and opcode
• Buses

  • a set of parallel wires that connect two or more components in the CPU
  • there are three buses in the CPU, collectively called the system bus
• Width of Buses

  • the number of parallel wires the bus has
  • directly proportional to number of bits that can be transferred simultaneously
  • typically 8, 16, 32 or 64 wires wide
• The 3 Buses

  • data bus
  • control bus
  • address bus
• Data Bus

  • bi-directional bus
  • used for transporting data and instructions between components
• Address Bus

  • used to transmit memory addresses specifying where data is to be sent or retrieved
  • width is proportional to number if addressable memory locations
• Control Bus

  • bi-directional
  • transmits control signals between internal and external components
  • coordinates use of other buses and provides status info between components
• Control Signals

  • bus request
  • bus grant
  • memory write
  • memory read
  • interrupt request
  • clock
• Bus Request

  • shows that a device is requesting use of data bus
• Bus Grant

  • shows that CPU has granted access to data bus
• Memory Write

  • data is written into addressed location using control bus
• Memory Read

  • data is read from specific location to be placed onto data bus
• Interrupt Request

  • shows that a device is requesting access to CPU
• Clock

  • used to synchronise operations
• Bi-Directional Bus

  • bits can be carried in both directions
• Fetch-Decode-Execute Cycle (FDE)

  • the sequence of operations that are completed in order to execute an instruction
• Fetch Phase (FDE)

  • address from the PC is copied to MAR
  • instruction held at address is copied to MDR by data bus
  • simultaneously, the contents of the PC are increased by 1
  • value held in MDR is copied to CIR
• Decode Phase

  • the contents of CIR are split into operand and opcode
• Execute Phase

  • the decoded instruction is executed
• Factors Affecting CPU Performance

  • clock speed
  • number of cores
  • amount of cache memory
  • type of cache memory
• Clock Speed

  • determined by system clock
  • time taken for one clock cycle to complete
• Number of Cores

  • computer with multiple cores can complete more than one FDE cycle at any given moment
• Core

  • an independent processor that can run its own FDE cycle
• Cache Memory

  • CPU's onboard memory
  • instructions fetched from main memory are copied to cache so, if needed again, can be accessed quicker
  • as cache fills, unused instructions are replaced
• Level 1 Cache

  • very fast memory cells with small capacity
  • 2-64KB
• Level 2 Cache

  • relatively fast memory cell, with a medium sized capacity
  • 256KB-2MB
• Level 3 Cache

  • much larger and slower memory cell
• Von Neumann Architecture

  • includes all basic components of computer and processor in which a shared memory and shared data bus is used for both data and instructions
  • built on stored program concept
• Von Neumann Architecture - Components

  • single control unit
  • ALU
  • registers
  • memory units
• Harvard Architecture

  • has physically separate memories for instructions and data, more commonly used with embedded processors