1.1.1 - Structure and functions of the processor

• Arithmetic Logic Unit (ALU)


  -Carries out the calculations and logical decisions-results are stored in the accumulator (ACC)
• Control Unit (CU)


  Decodes instructions and sends out control signals
• Register


  -small piece of memory, used for storing data within the processor
• Program Counter (PC)


  -stores the addres of the next instruction to be fetched-incremented to identify next instruction to be fetched in FDE cycle-can also be changed by branch statement-allows programs to be executed in correct sequence-contents copied to the MAR at start of FDE
• Accumulator (ACC)


  -temporary storage for data being processed-holds all input/output-checked for conditional branching (e.g. BRZ/BRP)-data from memory can be loaded/copied into the ACC (LDA)-data in the ACC can be stored/copied to a memory location (STA)
• Memory Address Register (MAR)


  -contents of the PC are copied here in order for the processor to access the next instruction
• Memory Data Register (MDR)


  -stores the data or instruction being fetched from/copied to memory
• Current Instruction Register (CIR)


  -stores the most recently fetched instruction being (or waiting to be) executed
• Buses


  -communication channels/links through which data can be sent around the computer
• Data bus

  -carries data between the processor and memory
• Address bus


  -carries the address of the memory location being read from or written to
• Control bus


  -sends control signals from the control unit to control the computer
• Fetch-Decode-Execute Cycle


  -sequence of operations that are completed in order to execute an instruction
• Fetch


  The PC is loaded with 0The value from the PC (0) is copied to the MAR The data from the MAR (0) is sent across the address bus with the instruction to read the data sent across the control bus The data from that location in memory (0) is sent down the data bus to the MDR The PC is incremented by 1
• Decode


  -control unit decodes the instruction in the CIR
• Execute


  1. If a value is being inputted (INP) the ACC will store the value

  2. If a value is being outputted (OUT) this will be the value currently in the ACC

  3. If a value is loaded from RAM (LDA) this will be sent across the data bus from RAM (in the address location in the MAR) to the MDR

  4. If a value is to be stored (STA) it will take the value from the ACC, send it to the MDR and then send it across the data bus to RAM (to the address location in the MAR)

  5. If a value is being added to or subtracted from another value (ADD/SUB)

  6. If the LMC code is to branch (BRA/BRZ/BRP) the comparison will take place in the ALU
• High performance CPU might have:


  -multiple cores-high clock speed-large cache-ability to use pipelining
• Clock speed


  -Higher clock speed gives more cycles per second meaning more instructions can be executed per second, so the program takes less time to run-measures in Gigahertz (GHz, 1,000,000,000 pulses per second)-one operation carried out each pulse
• Cores


  -distinct processing unit on the CPU-carries out instructions (FDC)-overall controlled by the processor-instructions can be carried out simultaneously in multi-core systems-different cores can run different applications
• Multiple cores


  -can execute several programs simultaneously-or execute different parts of the same program in parallel-each core acts as a separate processing unit-multi-core processor: has more than one processing unit which can independently process instructions at the same time
• Cache


  -built into the processor-fast memory, distance to processor reduced. faster than RAM-needed as RAM slower than processor-more expensive than RAM-becomes slower as size increases, so different levels (often 3) used-when data needed, smallest cache (fastest) searched first, then larger and larger until RAM is searched
• Large cache memory


  -gives more space for data/instructions in cache memory-means slower RAM needs to be accessed less frequently-accessing cache quicker than accessing RAM
• Pipelining


  -concurrent processing of multiple instructions-one instruction can be fetched while previous is being decoded, and one before is being executed-in case of branch pipeline is flushed-increases speed of execution, more instructions can be carried out in a set amount of time/less time to execute same number of instructions-increases speed/performance/efficiency of the computer/program, quicker for program to complete-reduces/removes latency, CPU not idle while waiting for next instruction-all parts of the processor used at any instance in time
• Limitations of pipelining


  -not always possible to accurately predict what instruction needs to be fetched and decoded next-e.g. if 2nd instruction when executed branches to another instruction it has to 'flush the pipes' of the existing instructions-the more often the pipeline has to be flushed, the less of a benefit pipelining is.
• Von Neumann architecture


  -processor architecture-both data and instructions share the same memory-both data and instructions stored in the same format-single set of buses/same bus for data and instructions to connect CPU to memory and I/O-single control unit-single ALU-follow FDC cycle, can only fetch either instructions or data at one time-uses special registers within CPU-based on stored program concept
• Harvard architecture


  -separate memory for data and instructions/multiple memory units-different (sets of) buses for instructions and data, instructions and data can be accessed concurrently-useful for (for example) a smart washing machine: fixed instruction size, no need for memory to be shared between data and instructions, removes need for secondary storage, instructions would never be changed
• Features not part of standard Von Neumann architecture contemporary CPUs may have in order to improve performance:


  -2 separate areas of memory and different (sets of) buses, 1 for data and 1 for instructions, so that data and instructions can be accessed concurrently-pipelining-use of cache-virtual cores/hyper-threading, treating a single physical core as two virtual cores-multiple cores-onboard graphics, built in circuitry for graphics processing