The processor

• Processor/Central Processing Unit (CPU)


  The internal hardware component of the computer that is responsible for executing the instructions of programs
• ALU


  Responsible for performing arithmetic calculations and logical operations
• Operations performed by the ALU

  • Addition, subtraction, multiplication, division
  • Logical bitwise operations, such as AND, OR, NOT, and XOR
  • Comparisons between values, such as greater than, less than, equal to
  • Shifting binary patterns to the left or right
• Control unit (or program control unit)

  In charge of organising the sequence in which program instructions are executed, followed by decoding the instructions
• Tasks of the control unit

  • Uses control signals to enable data to be read (i.e. loaded) from and written (i.e. stored) to the main memory
  • Decodes every instruction that the processor will execute to determine what needs to be done
  • Organises the sequence of micro-operations that need to be performed in order to carry out an instruction
  • Uses control signals to determine the operation the ALU will carry out at each instance
• System clock/Clock


  Generates regular clock pulses by emitting a signal that continuously oscillates between a low (or '0') and a high (or '1') state
• Rising edge


  A change from a low (or '0') state to a high (or '1') state
• Falling edge


  The opposite of a rising edge
• Clock period


  The time taken between two sequential rising edges, corresponds to one clock cycle
• Every operation of the processor typically requires a number of clock cycles to complete, the number of cycles is specific to each type of processor
• Clock rate/Clock frequency/Clock speed

  The number of clock cycles that can be completed in one second, measured in Hz, typically MHz and GHz
• Clock frequency = 1 / clock period
• A data transfer is generally described as one operation, but in reality it can take many clock cycles to achieve
• Reading a memory location

  1. Processor sends a read request via the control bus

  2. Processor sends the address of the memory location via the address bus

  3. Processor receives the contents of that memory location via the data bus, after a number of clock cycles
• Writing to a memory location

  1. Processor sends a write request via the control bus

  2. Processor sends the address of the memory location via the address bus

  3. Processor sends the data that needs to be stored via the data bus
• Registers


  Locations of computer memory within the processor that provide extremely fast access, should not be confused with the addressable locations of main memory
• General-purpose registers


  • Used to keep the results of the intermediate calculations that are produced as part of a larger computation
• Dedicated/special-purpose registers


  • Program counter (PC)
  • Current instruction register (CIR)
  • Status register (SR)
  • Memory address register (MAR)
  • Memory buffer register (MBR)/memory data register (MDR)
  • Accumulator
• Fetch-decode-execute cycle


  The three main stages the processor goes through to carry out an instruction, repeated over and over again for every instruction of every program
• Fetch stage


  1. Program counter contents copied to memory address register

  2. Instruction fetched from memory to memory buffer/data register

  3. Program counter incremented

  4. Instruction copied to current instruction register
• Decode stage


  Control unit decodes the instruction in the current instruction register
• Execute stage


  Instruction is executed, any required data fetched, calculation performed by ALU, result stored
• Registers


  Locations of computer memory within the processor that provide extremely fast access
• Registers should not be confused with the addressable locations of main memory
• Types of registers


  • General-purpose registers
  • Dedicated/special-purpose registers
• General-purpose registers


  • Used to temporarily store and access the results of operations
  • Connected to the ALU and used to keep the results of the intermediate calculations that are produced as part of a larger computation
• Dedicated/special-purpose registers


  • Used for a specific purpose
  • Registers used in the fetch-decode-execute cycle
• Program counter (PC)


  Holds the address of the next instruction to be executed by the processor
• Current instruction register (CIR)


  Holds the current instruction that the processor is executing
• Status register (SR)


  • Used to store information about the result of the last instruction that the ALU executed
  • Each bit within the status register acts as a flag to indicate if an error or exception has occurred within the process, or to enable or disable interrupts to be raised
• Memory address register (MAR)


  Temporarily holds the address of the memory location (in main memory) that the processor needs to access, either to read from (i.e. load data) or write (i.e. store data) to
• Memory buffer register (MBR)/memory data register (MDR)


  Temporarily holds the data (data values or instructions) that are read from or written to the main memory
• Accumulator


  • Stores the result of any calculation processed by the ALU
  • The processor accesses other general-purpose registers where temporary values are stored while calculations are completed
  • Any result resides in the accumulator
• Every time the processor carries out an instruction, it goes through three main stages: it fetches, decodes, and executes the instruction. These stages form the fetch-decode-execute cycle — or fetch-execute cycle or instruction cycle — because they are repeated over and over again for every instruction of every program that is run inside a computer.
• Before the fetch-decode-execute cycle can take place, a program’s instructions need to be ‘ready’ to be carried out. This means that:

  1. The program instructions have been translated into machine code
  2. The program instructions have been loaded (from secondary storage) into the main memory (RAM)

  At the end of a cycle for each instruction, the processor checks the status register to see if an error, exception, or interrupt needs to be handled. For example, if an interrupt is indicated, the control might be transferred to the corresponding interrupt service routine.
• All components are connected to the control unit, which demonstrates that the control unit is responsible for setting the pathways for the exchange of data between the internal components. For example, the control unit is in charge of directing data values from general-purpose registers as inputs to the ALU, retrieving the output of the ALU, and saving it into the accumulator.
• The processor communicates with RAM using two special-purpose registers: the memory data/buffer register and the memory address register. However, this does not mean that the general-purpose registers or the accumulator can't exchange data with the main memory directly. This depends on the type of instruction that is being executed and it is also managed by the control unit.
• Clock cycles per operation


  The number of clock cycles required to complete a data transfer operation in a computer
• In the model of a computer, a data transfer is generally described as one operation. In reality, it can take many clock cycles to achieve a data transfer from one component to another.
• Reading a memory location

  1. Processor sends read request via control bus

  2. Processor sends address of memory location via address bus

  3. Processor receives contents of memory location via data bus after a number of clock cycles