1. Processor completes the fetch-decode-execute cycle of the instruction it was running when it received the interrupt
2. Current contents of the processor registers (including the program counter) are saved to memory
3. Origin of the interrupt is identified so that the appropriate ISR is called
4. Lower-priority interrupts are put on hold to allow the ISR to finish running
5. Program counter is updated with the address of the first instruction of the ISR
6. ISR completes its execution
7. Processor registers are reloaded with the values that were saved to memory
8. Lower-priority interrupts that were put on hold are re-established
9. Program counter is set to point to the address of the next instruction that needs to be executed in the program that the processor was running when it received the interrupt