Comp sci

• What are the main components of a processor?

  The main components are the Arithmetic and Logic Unit, Control Unit, and Registers.
• What are the types of registers in a CPU and their purposes?

  • Program Counter (PC): Holds the address of the next instruction to be executed.
  • Accumulator (ACC): Stores the results from calculations.
  • Memory Address Register (MAR): Holds the address of a location to be read from or written to.
  • Memory Data Register (MDR): Temporarily stores data that has been read or needs to be written.
  • Current Instruction Register (CIR): Holds the current instruction being executed, divided into operand and opcode.
• What is the purpose of the Arithmetic and Logic Unit (ALU)?


  The ALU completes all arithmetical and logical operations.
• What types of operations does the ALU perform?

  The ALU performs arithmetical operations like addition and subtraction, and logical operations like AND, OR, NOT, and XOR.
• What is the role of the Control Unit in a CPU?

  The Control Unit directs the operations of the CPU, managing data flow, accepting instructions, decoding them, and storing results back in memory.
• What are the three types of buses in a CPU?

  • Data Bus: Bi-directional bus for transporting data and instructions.
  • Address Bus: Transmits memory addresses for data retrieval or storage.
  • Control Bus: Bi-directional bus for transmitting control signals between components.
• What is the function of the Data Bus?

  The Data Bus is used for transporting data and instructions between components.
• How does the width of a bus affect data transfer?

  The width of the bus, which is the number of parallel wires, is directly proportional to the number of bits that can be transferred simultaneously.
• What is the purpose of the Current Instruction Register (CIR)?

  The CIR holds the current instruction being executed, divided into operand and opcode.
• What is the Fetch-Decode-Execute Cycle?

  • Fetch phase: Address from the PC is copied to the MAR, instruction is copied to MDR, PC is incremented, and MDR is copied to CIR.
  • Decode phase: Contents of CIR are split into operand and opcode.
  • Execute phase: The decoded instruction is executed.
• What factors affect the performance of a CPU?


  The factors affecting CPU performance are clock speed, number of cores, and cache memory.
• What is clock speed in relation to CPU performance?

  Clock speed is the time taken for one clock cycle to complete, determined by the system clock.
• How does the number of cores affect CPU performance?

  A computer with multiple cores can complete more than one fetch-execute cycle at any given time, potentially doubling performance with dual cores.
• What are the types of cache memory and their properties?

  • Level 1 Cache: Very fast memory cells with a small capacity (2-64KB).
  • Level 2 Cache: Relatively fast memory cells with a medium capacity (256KB-2MB).
  • Level 3 Cache: Much larger and slower memory cells.
• What is Von Neumann architecture?

  • Includes a single control unit, ALU, registers, and memory units.
  • Uses shared memory and shared data bus for both data and instructions.
  • Built on the stored program concept.
• What is Harvard architecture?

  • Has physically separate memories for instructions and data.
  • Commonly used with embedded processors.
  • Allows optimization of memory sizes and characteristics.
• What are the advantages of Von Neumann and Harvard architectures?

  Advantages of Von Neumann:

  • Cheaper to develop due to simpler control unit design.

  Advantages of Harvard:

  • Quicker execution as data and instructions can be fetched in parallel.
  • Programs can be optimized in size.
• What is contemporary processor architecture?

  • Uses a combination of Harvard and Von Neumann architectures.
  • Von Neumann is used for main memory operations, while Harvard is used to divide cache into instruction and data cache.
• What is pipelining in a processor?

  Pipelining is the process of completing the fetch, decode, and execute cycles of three separate instructions simultaneously.
• What are the two types of pipelining?


  The two types of pipelining are instruction pipelining and arithmetic pipelining.
• What is the effect of pipelining on CPU efficiency?


  Pipelining reduces the amount of the CPU that is kept idle by overlapping instruction processing.
• What happens during the fetch phase of the Fetch-Decode-Execute Cycle?

  During the fetch phase, the address from the PC is copied to the MAR, the instruction at that address is copied to the MDR, the PC is incremented, and the MDR is copied to the CIR.
• What happens during the decode phase of the Fetch-Decode-Execute Cycle?

  During the decode phase, the contents of the CIR are split into operand and opcode.
• What happens during the execute phase of the Fetch-Decode-Execute Cycle?

  During the execute phase, the decoded instruction is executed.
• Stack


  A data type that uss LOFO principle
• queue


  a data type that uses FIFO principle
• operations of a stack


  push() = puts an item ontop

  push() = removes top item

  peek()= to look at the top item but not removing it
• what does LIFO mean?


  last in first out
• what does FIFO mean?


  first in first out
• what is the format called when binary can be negative and can be used for arithmetic 


  Twos complement
• step by step to twos complement for -11:

  first find the normal binary value for the positive value: 00001011 = 11

  then start at the least significant bit and read across until you reach a 1.

  next keep the first 1 and any 0’s before and invert the rest of the digets so - 11 would be:

  11110101
• unsigned interger:

  positive

  stored as pure binary

  stored as 8 bits

  eg 131 :

  10000011
• signed or sign and magnitude:

  the most significant bit is what determines its positive or negative

  0 = positive

  1 = negative

  eg 77:

  01001101

  but -33:

  10100001
• binary arithmetic rules:

  0 + 0 =0 no carry

  1+1 =2 0 1 carry

  0+1= 1 no carry

  1+0 =1 no carry

  and 1+1 and 1 carry = 1 carry 1
• Flat file


  Single table / entity
• data redundancy 


  repetition
• data integrity


  the correctness of the data
• 1NF


  a table is in first normal form when there are no repeating attributes to groups of attributes
• 2NF


  when in this there should be no partial key dependencies
• partial key dependencies


  Should be no repeats with the primary key