CHAP 4

• Computer architecture


  The basic structure and components of a computer system
• Basic computer architecture components

  • Central Processing Unit
  • Memory
  • I/O interfacing circuit
• Processor system operation


  1. Fetch next instruction

  2. Decode instruction

  3. Execute

  4. Write result
• Central Processing Unit (CPU)


  • Controls system operations
  • Performs arithmetic and logic operations
• CPU components


  • Arithmetic logic unit
  • Registers
  • Control unit
• Bus


  A common group of wires that interconnect components in a computer system
• Types of buses


  • Address bus
  • Data bus
  • Control bus
• Address bus


  Unidirectional, determines the amount of memory that can be accessed (memory capacity)

  
• Data bus


  Bidirectional, contains the information to be transferred between CPU and memory

  
• Control bus


  Signals to control the microprocessor system
• Arithmetic Logic Unit (ALU)


  • Performs arithmetic operations (+, -, *, /)
  • Performs logic operations (NOT, AND, OR, XOR)
  • Performs shift and rotate operations
• Control Unit


  • Controls the movement of data between CPU and memory or I/O
  • Decodes the instructions and issues the commands to the ALU
• Registers


  • Storage in the CPU
  • Limited in numbers
  • Used for temporary storage of data that the ALU is processing
  • Data in the registers can be quickly accessed by the CPU
• CPU operation


  1. Fetch next instruction

  2. Decode instruction

  3. Execute

  4. Write result
• 8086 architecture


  • Divided into two independent functional units: Bus Interface Unit (BIU) and Execution Unit (EU)
  • BIU controls the transfer of instructions, address and data on the internal bus to the EU, and the transfer of data between the processor, external memory and I/O
  • BIU calculates the effective address of the memory
  • BIU has an instruction queue (IQ) of 6 bytes
  • EU informs BIU where to fetch the next instruction or data
  • EU performs Fetch, Decode, Execute and Write
• Memory types


  • Primary memory (ROM, RAM)
  • Secondary memory (Hard disk, DVD ROM, Thumb drive)

  
• Non-volatile memory types


  • ROM
  • EPROM
  • FLASH

  
• Volatile memory types


  • SRAM
  • DRAM

  
• SRAM


  Static, faster, low capacity (higher cost)
• DRAM


  Dynamic, slower, high capacity (lower cost), needs refresh
• Memory addressing


  Address bus determines the amount of memory that can be accessed
• Memory write cycle


  1. Valid address

  2. Data written to memory
• Memory read cycle


  1. Valid address

  2. Data from memory

  
• Memory connection


  Different memory types (ROM, RAM, etc.) connected to the microprocessor using address bus, data bus, read/write control signals, and chip select

  
• A18 and A19


  Can further provide 16 possible combinations of memory locations
• Memory Decoding Example


  1. Address Bus A13 - A0

  2. Data Bus D7 - D0

  3. RD

  4. WR

  5. IO/M

  6. Address Bus A19 - A14

  
• Memory Chips


  • RAM0 (16K)
  • RAM1 (16K)
  • RAM2 (16K)
  • RAM3 (16K)

  
• Decoding Circuit


  Selects the appropriate memory chip based on the address

  
• Address Range


  • 000000 to 00FFFF
  • 010000 to 01FFFF
  • 020000 to 02FFFF
  • 030000 to 03FFFF
  • 0F0000 to 0FFFFF
• Memory Bank


  64KB of memory created by combining 4 x 16KB memory chips
• Memory Decoding Example - Putting 4 x 16KB memory chips together

  1. Create a 64kB memory bank

  2. The upper four unused address lines can select 16 blocks of 64 kB each

  
• Memory Chip Addresses


  • RAM0 - 010000 to 013FFF
  • RAM1 - 014000 to 017FFF
  • RAM2 - 018000 to 01BFFF
  • RAM3 - 01C000 to 01FFFF

  
• Memory Decoding Example - Decoder Circuit

  Simple way to design a decoder is using AND gates
• Timing Diagram and Hardware Circuit when CPU executes MOV AL,[423CH]

  1. Valid Address

  2. Data from Memory

  3. CLK

  4. Address

  5. Data

  6. RD

  
• Assume DS is 1000H and memory location [1000:423CH] contains 78H
• The address 1423CH will cause the decoding circuit to select RAM1 since it has the address range of 14000 to 17FFF
• Decoder IC 74LS138


  • E3
  • E2
  • E1
  • S2
  • S1
  • S0
  • Y7
  • Y6
  • Y5
  • Y4
  • Y3
  • Y2
  • Y1
  • Y0
• 74LS138 Decoder IC


  1. 8 line decoder, Active LOW outputs
• Using a decoder IC can help in simplifying decoder circuitry
• I/O Devices


  • Speaker circuit
  • Keyboard circuit
  • Monitor circuit
  • Microphone
  • Mouse