COAR

• Pentium


  Brand name of many of Intel's x86 compatible microprocessors

  
• Original Pentium CPU


  • Released in 1993
  • Intel's fifth-generation microarchitecture

  
• 8088 Processor


  Eight bits (data) CPU with 1 mega byte of memory space (20 bits)
• 80386 Processor


  • Introduced: 1985
  • Initial clock speed: 16 MHz
  • Number of transistors: 275,000
  • Circuit line width: 1.5 micron
  • Memory: 4G or 32 bits address
  • Data bus: 32 bits
  • No internal cache
  • No FPU

  
• 32 bit Registers


  The original 16 bits registers are extended to 32 bits. The register AX becomes EAX.
• 80386 instructions using 32 bits registers


  • MOV EAX,12345678H
  • ADD EAX,EBX
  • MOV [ESI],AL
• 32 bit Memory Interface


  The 32 bits memory is organized into 4 banks of 8 bits each. Each byte will have an address so that they can be accessed individually.
• Accessing 32 bit memory


  • MOV AL,[00000004h] (bank 0 enabled, others disabled)
  • MOV AX,[00000004h] (banks 0 and 1 selected)
  • MOV EAX,[00000004h] (all banks selected)
  • MOV AL,[00000002h] (only bank 2 enabled)
• Pentium Processor


  • Introduced: 1993
  • Initial clock speed: 66 MHz
  • Number of transistors: 3.1 million
  • Circuit line width: 0.8 micron
  • 64 bits data bus
  • Memory addressed in eight banks
  • Can get 64 bits in one read cycle while 80486 needs two reads
  • Internal registers and Execution units are still 32 bits

  
• Pentium Microarchitecture


  • Cache – 8K data & 8K instruction
  • Pipelining
  • Two integer processors – allow 2 instructions per clock cycle (superscalar)
  • Branch Prediction Logic
  • Software is upward compatible
  • FPU has an eight-stage pipeline

  
• Floating point operations


  FADD – Add floating point numbers<|>FMUL – Multiply<|>FDIV – Divide<|>FSQRT – Finds Square root<|>FSIN – Sine<|>FYL2X – Y log2 X
• Cache memory


  Small but fast memory used in between main memory and CPU to improve performance<|>Pentium contains two 8K-byte cache memories (data and instructions)
• Advantages of separate data and instruction cache

  • Allows processor to fetch instructions and data simultaneously
  • Instruction caches are read-only and have simpler design
  • Prevents data intensive program from evicting instructions
• Superscalar architecture


  Use of multiple execution units to allow processing of more than one instruction at a time (parallel operations)<|>Pentium has three execution units (one floating point and two integer)
• Pentium Instruction execution


  1. Fetch

  2. Decode 1

  3. Decode 2

  4. Execute

  5. Write-back

  
• Pipelining


  Technique where multiple instructions are overlapped in execution
• Pentium 4 Processor


  • Introduced: year 2000
  • Initial clock speed: 1.5 GHz
  • Number of transistors: 42 million
  • Circuit line width: 0.18 micron
  • Hyper-pipelined technology (20 stage pipeline)
  • Rapid execution engine
  • Faster ALU (clocked at twice the frequency of the processor core)

  
• Execution Trace Cache


  • Saves decoding time by caching decoded instructions
• Hyperthreading


  • Ability to run two threads of code simultaneously
• Itanium 2 Processor


  • Introduced: year 2002
  • Initial clock speed: 1 GHz
  • Number of transistors: 220 million
  • Circuit line width: 0.18 micron
  • IA-64 architecture
  • 128 integer registers
  • Implements predication, speculation, and branch prediction under compiler control

  
• Intel Core Duo


  • Introduced: Jan 5, 2006
  • Process: 65 nanometer
  • Transistor Count: 151 million
  • Clock Speed: 1.66 to 2.33G
  • L1 Cache: 32KB inst, 32KB data
  • L2 Cache: 2MB

  
• Instead of improving the core design of the CPU, Intel decided to put multiple cores in a die. This started with the Duo Core CPU.

  
• Future Trends: Clock speed improvements are slow due to physical limitations. Difficult to further optimize a single core for performance. Multi-cores: Each new processor generation will accommodate more cores, e.g. Quad Core CPU. Processing in Memory.