CHAP 5

• Computer architecture


  The fundamental organization and design of a computer system
• Input/output (I/O)


  The communication between a computer and the outside world
• IO basics


  • Programmed IO
  • Basic IO connection and operation
  • Interrupt driven IO
  • Direct memory access
  • External interconnection standards
• Computer systems


  • Made of three fundamental elements: the processor, a set of memory modules and a set of I/O modules
  • Each module interfaces to the system bus or central switch and controls one or more peripheral devices
  • An I/O module contains logic for performing communication between the peripheral and the bus
• External devices


  • Human readable (display unit, printer)
  • Machine readable (hard disk, sensors, actuators, robot arm etc)
  • Communication (another computer)
• Programmed IO


  1. Processor issues a command to the I/O module

  2. Processor waits until the I/O operation is complete

  3. Processor executes a program that enables direct control of the I/O operation

  4. Data are exchanged between the processor and the I/O module

  
• Basic IO connection


  Uses an I/O decoder to access I/O devices instead of memory
• Basic IO operation


  1. Fetch instruction

  2. Return instruction

  3. Execute instruction (receive data from IO device)

  4. Device puts data to data bus, CPU takes data and places to register

  
• Memory vs IO


  Memory addresses are different from I/O addresses<|>I/O devices are accessed using the IO/M control signal
• Simple input device


  • 8 switches connected to input port at address 81h
  • Assembly code to read switch status: IN AL,81H
• Simple output device


  • 8 LEDs connected to output port at address 42h
  • Assembly code to turn on all LEDs: MOV AL,0FFH, OUT 42H,AL
• We can make a tristate buffer to build an input device
• CPU (simulated by Arduino) will enable individual ports one data time and capture their data
• Interrupt driven I/O


  Processor issues an I/O command to a module and then continues to do some other work<|>The I/O module will then interrupt the processor to request service when it is ready to exchange data with the processor<|>The processor then executes the data transfer and resumes its former processing

  
• Interrupt driven I/O operation

  1. I/O module receives READ command from the processor

  2. I/O module captures data from an associated peripheral

  3. I/O module signals an interrupt to the processor

  4. Processor saves the context of the current program

  5. Processor processes the interrupt (reads data from the I/O module)

  6. Processor restores the context of the program it was working and resumes execution

  
• Interrupt processing


  • The status of the processor contained in the program status word (PSW)
  • The location of the next instruction to be executed contained in the program counter
  • These are pushed onto the system control stack

  
• Techniques for handling multiple interrupts

  • Multiple interrupt lines
  • Software poll
  • Daisy chain (hardware poll, vectored)
  • Bus arbitration (vectored)
• Interrupt-Service routine


  1. Polls each I/O module to determine module causing interrupt

  2. Processor branches to a corresponding Service routine specific to that device

  
• Daisy chain (vectored interrupt method)


  Hardware polling method where all I/O modules share a common interrupt request line and the interrupt acknowledge line is daisy chained through the modules
• Daisy chain (vectored interrupt method)

  1. Upon sensing an interrupt, processor acknowledges interrupt that propagates through I/O modules until it gets to the requesting module

  2. Module responds by placing a word (vector) containing the address/unique identifier of the module on the data lines

  3. Processor uses the vector to start matching service routine

  
• Bus arbitration


  1. Technique that uses vectored interrupts where an I/O module gains control of the bus before it can raise the interrupt request line

  2. Only one module can raise the line at a time

  3. When the interrupt detected, processor responds with acknowledge

  4. The requesting module then places its vector on the data lines

  
• It is possible to provide a way of assigning priorities among devices in these techniques
• The processor just picks the interrupt line with the highest priority first
• Interrupt driven I/O


  Restricted, Non-Sensitive
• Intel processor


  Provides a single Interrupt Request (INTR) and a single Interrupt Acknowledge (INTA) line
• 82C59A


  External interrupt arbiter used to handle variety of devices and priority structures

  
• 82C59A is not available as a separate chip anymore, but is still provided by the Platform Controller Hub or Southbridge chipset on modern x86 motherboards

  
• Interrupt-driven I/O


  • More efficient than simple programmed I/O though it still requires the active intervention of the processor
  • I/O transfer rate is limited by the speed of the processor and device
  • Processor is tied up in managing an I/O transfer; a number of instructions must be executed for each I/O transfer
• Direct memory access (DMA)


  An additional module on the system bus that mimics the processor and overtakes control from the processor to transfer data to/from memory over the system bus directly
• Direct memory access (DMA)


  1. Once the DMA controller is granted access to the system bus by the CPU, it transfers all bytes of data in the data block before releasing control of the system buses back to the CPU

  2. This transfer mode is called Burst mode
• Direct memory access (DMA)


  Another method is to use the bus only when the processor does not need it, referred to as cycle stealing, because the DMA module in effect steals a bus cycle
• Direct memory access (DMA)


  When the processor wishes to read or write a block of data, it issues a command to the DMA module sending information about the read/write request, the address of the I/O device, the starting memory location, and the number of words to read/write
• Serial transfer


  Slower data transfer, more wires required
• Parallel transfer


  Faster data transfer, fewer wires required
• Intel 8255 Programmable Peripheral Interface (PPI) chip


  Developed by Intel in 1970s, provides 24 parallel input/output lines with a variety of programmable operating modes

  
• UART 8250


  IC for interface for serial communications, commonly used in PCs and related equipment such as printers or modems
• USB (Universal Serial Bus)


  Widely used for peripheral connections, default interface for slower speed devices but also used for high-speed I/O, allows hot swapping, configurations done automatically
• USB generations


  • USB 1.0: Low Speed 1.5 Mbps, Full Speed 12 Mbps
  • USB 2.0: 480 Mbps
  • USB 3.0: Up to 4 Gbps
  • USB 3.1: 9.7 Gbps
  • USB4: 20 Gbps
• Thunderbolt


  High-speed peripheral connection technology, combines data, video, audio, and power into a single connection, provides up to 10 Gbps throughput and up to 10 watts of power
• Ethernet chronology


  • 1983: 10 Mbps
  • 1995: 100 Mbps
  • 1998: 1 Gbps
  • 2003: 10 Gbps
  • 2010: 40 Gbps and 100 Gbps
  • 2022 roadmap: 800 Gbps and 1.6 Tbps