FDE Cycle

• Fetch:

  1. Address of next instruction transferred from PC to MAR
• Fetch:

  2. Content of MAR transferred to main memory via address bus
• Fetch:

  3. The instruction is sent from main memory to MBR via the data bus
• Fetch:

  4. PC increments by 1
• Fetch:

  5. Contents of MBR copied to CIR
• Decode:

  1. Content of CIR decoded by control unit
• Decode:

  2. Decoded instruction split into opcode/operand
• Execute:

  1. Data is passed to registers
• Execute:

  2. Any additional data required is fetched from main memory
• Execute:

  3. Instruction carried out by ALU
• Execute:

  4. Results of instruction are stored in main memory or general purpose registers
• Check for interrupts:

  Between each fetch and execute stage, the contents of the status register is checked for changes that could signify an interrupt.
• Fetch:

  1. Address of next instruction transferred from PC to MAR
  2. Content of MAR transferred to main memory via address bus
  3. The instruction is sent from main memory to MBR via data bus
  4. Content of MBR copied to CIR
  5. PC increments by 1
• Decode:

  1. Content of CIR decoded by CU
  2. Decoded instruction split into opcode and operand
• Execute:

  1. Data is passed to registers
  2. Any additional data, if required, is fetched
  3. Instruction carried out by ALU
  4. Results of instruction are stored in main memory or general purpose registers