M8

• Semiconductor Fabrication Process

  The process of manufacturing semiconductor devices, such as transistors and integrated circuits, from raw materials
• Four General Processes

  • Materials Preparation
  • Wafer Preparation
  • Wafer Fabrication
  • Assembly
• Materials Preparation

  • Silicon is extracted from sand (silicon dioxide, SiO2)
  • The silicon is then purified to obtain electronic-grade silicon, having an impurity level of no more than several parts per million
• Extraction of Silicon

  1. Silicon is commercially prepared by the heating of high-purity silica in an electric arc furnace using carbon electrodes

  2. At temperatures over 1900 °C, the carbon reduces the silica to silicon

  3. Liquid silicon collects in the bottom of the furnace and is then drained and cooled

  4. The silicon produced via this process is called metallurgical grade silicon and is at least 99% pure

  5. Using this method, silicon carbide, SiC, can form. However, provided the amount of SiO2 is kept high, silicon carbide may be eliminated
• Purification of Silicon - Physical method

  1. Zone melting - a process wherein a small portion (zone) of the silicon rod is heated through magnetic induction until it melts

  2. The heater is slowly moved down the length of the rod, keeping a zone molten as the silicon cools and resolidifies behind it

  3. Since most impurities tend to remain in the molten region rather than resolidify, when the process is complete, most of the impurities in the rod will have been moved into the end that was the last to be melted

  4. This end is then cut off and discarded, and the process repeated if a still higher purity was desired
• Purification of Silicon - Chemical method

  1. The Siemens process - high-purity silicon rods are exposed to trichlorosilane at 1150 °C

  2. The trichlorosilane gas decomposes and deposits additional silicon onto the rods, enlarging them

  3. Silicon produced from this and similar processes is called polycrystalline silicon

  4. Polycrystalline silicon typically has impurity levels of 1 part per billion or less

  
• Polysilicon Ingot

  • The polycrystalline silicon tubes refined by dissolving in hydrofluoric acid (HF) producing polysilicon ingots
  • Polycrystalline silicon has randomly oriented crystallites, with electrical characteristics not ready for device fabrication

  
• Doping Poly-Silicon

  1. Chemical Vapor Deposition - a vessel which is evacuated and that contains "U" shaped arrangements of slim Si rods which can be heated from an outside heating source

  2. As soon as the temperature is high enough (roughly 1000 °C) to provide sufficient conductivity, by passing an electrical current through it

  3. An optimized mix of SiHCl3 (Trichlorosilane), H2 and doping gases like AsH3 or PH3 are admitted into the reactor
• Silicon Crystal Growth - Czochralski method

  1. A 'seed' is slowly rotated and lowered into the silicon 'melt'

  2. Silicon crystals form around the seed in a manner dictated by the seed's crystal structure

  3. As the seed is pulled from the melt, a small amount of liquid silicon goes with it. As it cools, a single silicon crystal ingot is formed

  4. The process continues until an ingot of desired dimensions is achieved
• Single Crystalline Ingot

  • The ingot diameter is determined by a combination of temperature and extraction speed
  • Most ingots produced today are 150mm (6") and 200mm (8") in diameter
  • For the most current technology, 300mm (12") and 400mm (16") diameter ingots are being developed
• Crystal Orientation and Ingot Characterization

  • Single-crystal silicon ingots are characterized by the orientation of their silicon crystals
  • Before the ingot is cut into wafers, one or two "flats" are ground into the diameter of the ingot to mark this orientation
  • This will be used in orienting the wafer into the exact position for later procedures

  
• Wafer Flats

  • Wafer flats tell you the doping type of the wafer (either p-type or n-type) and the crystal orientation on the wafer (either {100} or {111})
  • Consider that all wafers after processing look alike, so there is no way to determine what type of wafer you have!
• Crystal (or lattice) Orientation

  • The lattice orientation refers to the organized pattern of the silicon crystals in the wafer and their orientation to the surface
  • The orientation is obtained based on the orientation of the crystal that is placed into the molten silicon bath
  • The different orientations have different benefits and are used in different types of chips

  
• <100> and <111> Orientations

  • <100> orientation is used for MOS, Bi-CMOS, & GaAs types of chips
  • <111> orientation is used for Bipolar types of chips
• Preparing the Wafer

  1. The ingot is ground into the correct diameter for the wafers

  2. Then it is sliced into very thin wafers, usually done with an internal diameter (ID) diamond saw

  3. The edges are then rounded off to prevent chipping
• Wafer Lapping

  1. The sliced wafers are mechanically lapped using a counter-rotating lapping machine and aluminum oxide slurry

  2. This flattens the wafer surfaces, makes them parallel and reduces mechanical defects like saw markings
• Wafer Etching

  1. After lapping, wafers are etched in a solution of nitric acid / acetic acid or sodium hydroxide to remove microscopic cracks or surface damage created by the lapping process

  2. The acid or caustic solution is removed by a series of high-purity DI water baths
• Wafer Polishing

  The wafers are held in a hard ceramic chuck using either wax bond or vacuum and buffed with a slurry of silica powder, DI water and sodium hydroxide
• Wafer Cleaning

  1. Most wafer manufacturers use a 3-step process which starts with an SC1 solution (ammonia, hydrogen peroxide and DI water) to remove organic impurities and particles from the wafer surface

  2. Next, natural oxides and metal impurities are removed with hydrofluoric acid

  3. Finally, the SC2 solution, (hydrochloric acid and hydrogen peroxide), causes super clean new natural oxides to grow on the surface
• The Complete Silicon Process
• Chip Fabrication Process

  • Complete IC fabrication process has many individual processing steps (>100) and can take several weeks to carry out
  • Each process step accurately controlled in order to give acceptable overall result (high process yield)
  • For a typical IC chip of area 1cm × 1cm containing 1 million or more components each component in the order of fractions of a µms (human hair approximately 50µm diameter)
  • Patterning defines the component sizes - currently 0.13µm (130nm) - Deep Sub-micron technology
• Growth of Epitaxial Silicon

  1. The purpose of EPI growth is to create a layer with different, usually lower, concentration of electrically active dopant on the substrate

  2. This layer is of a much better quality than the slightly damaged or unclean layer of silicon in the wafer

  3. It is called the Epitaxial layer - where the actual processing will be done

  
• Epitaxial Layer (Epitaxy)

  • Very thin layers (1-10µm) of accurately controlled doped silicon is 'grown' onto the wafer in such a way that the crystal structure is continuous between the substrate and the epitaxial layer
  • Trichlorosilicane gas (SiHCl3) is admitted into a reaction chamber under high temperature which decomposes and deposits pure Si on the surface of the wafer (Siemens Process)
• Photolithography and Etching

  1. Process which effectively transfers the chip layout on a mask onto the silicon surface - has similarities to photographic printing

  2. Objective is to enable many (millions) of shapes to be printed on the wafer in one operation (with enormous cost benefits)

  3. Most important process as far as ensuring that the various components line up with each other and are interconnected correctly (determines line width)

  
• Photoresist Application

  1. A layer of photoresistive material is spread evenly on the surface of the wafer

  2. This layer dissolves upon exposure to ultraviolet light, leaving a pattern on the wafer's surface dictated by a mask
• Masking

  • A mask is a template that contains the pattern for the different layers to be made on the chip
  • The mask, together with a stepper, imposes the patterns on the wafer's surface (hundreds per wafer)
• The next steps...

  • Doping (Diffusion)
  • Ion Implantation
  • Deposition
  • Metallization
  • Etching
• Doping (Diffusion)

  Doping is accomplished by exposing the wafer to a dopant gas, under high temperature and pressure, depositing a layer of dopant material on the wafer's surface. These particles must then diffuse into the silicon
• Masking

  A layer of material spread evenly on the surface of the wafer that dissolves upon exposure to ultraviolet light, leaving a pattern on the wafer's surface dictated by a mask
• Mask

  A template that contains the pattern for the different layers to be made on the chip. The mask, together with a stepper, imposes the patterns on the wafer's surface (hundreds per wafer)

  
• Next steps after masking

  • Doping (Diffusion)
  • Ion Implantation
  • Deposition
  • Metallization
  • Etching
• Doping (Diffusion)

  1. Exposing the wafer to a dopant gas, under high temperature and pressure, depositing a layer of dopant material on the wafer's surface

  2. Diffusion (or solid state diffusion) is the process whereby a solid will physically diffuse itself into another solid in close contact with it due to the random thermal movement of atoms

  3. Essentially zero at room temperatures and up to 300-400ºC, over long periods at normal operating temperatures

  4. At high temperatures (>1,000ºC) diffusion increases considerably
• Ion Implantation

  1. Firing high energy atoms of the dopant elements, onto the silicon wafer

  2. The ions travel a small distance (typically <1µm) into the wafer before losing their energy and being absorbed

  3. Annealing process at temperatures of about 600ºC for a short time to repair the mechanical damage caused by the high energy ions and also to cause ions to fit into the silicon crystal lattice substitutionally
• Silicon Dioxide and Silicon Nitride

  • Dielectric materials used in IC processing for electrical insulation purposes and for passivation (final covering of all exposed areas of silicon)
  • Also used as dopant masks, and as dielectrics in capacitors
  • Easily formed by deposition or by heating the wafer at temperatures up to around 1,000ºC in the presence of relevant gases

  
• Polycrystalline Silicon (polysilicon)

  Formed by depositing silicon onto the wafer and is used as an interconnect between parts of the chip (highly doped in order to reduce resistance) or for passivation (undoped to increase its resistance)

  
• Aluminum and Other Metallization Layers

  • ICs contain a very large number of transistors and other components formed in the silicon wafer surface
  • The components have to be interconnected to form a working circuit using a low resistance material (metal) - usually aluminum - that is compatible with the silicon fabrication process (metallization)
  • Copper also now also used to reduce voltage drops and increase power levels
  • Polysilicon also used as it offers the ability to form extra layers relatively easily but its resistance is higher than a metal

  
• Etching

  1. After the layers (materials) have been deposited on the wafer's surface, we must remove some material on unwanted areas

  2. Process relies on the ability to accurately remove material such as silicon dioxide defined by photolithography

  3. Originally used acids or solvents of various types (known as wet etching) but had significant drawbacks

  4. A newer technique – dry etching, rectifies this problem
• Wet Etching

  Removed material in all directions (isotropic) thus removing the masking material also resulting in a change in the pattern dimensions from original layout/mask (undercutting)
• Dry Etching

  Anisotropic processes were developed, in which it only removed material in one direction (normally vertically) overcoming undercutting, giving a faithful representation of the mask pattern on the silicon wafer
• Backgrind and Wafer Wash

  1. Using composite grinding wheels, the thickness of the wafer is reduced to provide both a clean, uniform surface and a specified product thickness

  2. The wafer is then cleaned using a high pressure wash